522         { RTLIB::OEQ_F32, "__eqsf2vfp",    ISD::SETNE },  in ARMTargetLowering()
523         { RTLIB::UNE_F32, "__nesf2vfp",    ISD::SETNE },  in ARMTargetLowering()
524         { RTLIB::OLT_F32, "__ltsf2vfp",    ISD::SETNE },  in ARMTargetLowering()
525         { RTLIB::OLE_F32, "__lesf2vfp",    ISD::SETNE },  in ARMTargetLowering()
526         { RTLIB::OGE_F32, "__gesf2vfp",    ISD::SETNE },  in ARMTargetLowering()
527         { RTLIB::OGT_F32, "__gtsf2vfp",    ISD::SETNE },  in ARMTargetLowering()
528         { RTLIB::UO_F32,  "__unordsf2vfp", ISD::SETNE },  in ARMTargetLowering()
531         { RTLIB::OEQ_F64, "__eqdf2vfp",    ISD::SETNE },  in ARMTargetLowering()
532         { RTLIB::UNE_F64, "__nedf2vfp",    ISD::SETNE },  in ARMTargetLowering()
533         { RTLIB::OLT_F64, "__ltdf2vfp",    ISD::SETNE },  in ARMTargetLowering()
534         { RTLIB::OLE_F64, "__ledf2vfp",    ISD::SETNE },  in ARMTargetLowering()
535         { RTLIB::OGE_F64, "__gedf2vfp",    ISD::SETNE },  in ARMTargetLowering()
536         { RTLIB::OGT_F64, "__gtdf2vfp",    ISD::SETNE },  in ARMTargetLowering()
537         { RTLIB::UO_F64,  "__unorddf2vfp", ISD::SETNE },  in ARMTargetLowering()
597       { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
599       { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
600       { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
601       { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
602       { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
603       { RTLIB::UO_F64,  "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
614       { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
616       { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
617       { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
618       { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
619       { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
620       { RTLIB::UO_F32,  "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },  in ARMTargetLowering()
2011   case ISD::SETNE:  return ARMCC::NE;  in IntCCToARMCC()
2048   case ISD::SETNE:  in FPCCToARMCC()
5142                          SelectTrue, SelectFalse, ISD::SETNE);  in LowerSELECT()
5189   if (CC == ISD::SETUNE || CC == ISD::SETNE) {  in checkVSELConstraints()
5464       CC = ISD::SETNE;  in LowerSELECT_CC()
5623       CC = ISD::SETNE;  in OptimizeVFPBrcond()
5707       CC = ISD::SETNE;  in LowerBR_CC()
5719       (CC == ISD::SETEQ || CC == ISD::SETNE)) {  in LowerBR_CC()
5729     if ((CC == ISD::SETNE) != isOneConstant(RHS)) {  in LowerBR_CC()
5752        CC == ISD::SETNE || CC == ISD::SETUNE)) {  in LowerBR_CC()
6712       (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {  in LowerVSETCC()
6724     if (SetCCOpcode == ISD::SETNE)  in LowerVSETCC()
6738     case ISD::SETNE:  in LowerVSETCC()
6787     case ISD::SETNE:  in LowerVSETCC()
9157                      DAG.getCondCode(ISD::SETNE));  in LowerTruncatei1()
10299       CC = ISD::SETNE;  in LowerFSETCC()
17957            (CC == ISD::SETNE && Imm == 1) ||  in PerformHWLoopCombine()
17964            (CC == ISD::SETNE && Imm == 0) ||  in PerformHWLoopCombine()
18123     SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);  in PerformCMOVCombine()