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Searched refs:Rm (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb.td454 // ADD <Rm>, sp
466 // ADD sp, <Rm>
471 bits<4> Rm;
900 bits<3> Rm;
909 bits<3> Rm;
929 bits<3> Rm;
941 bits<3> Rm;
952 bits<3> Rm;
1144 bits<4> Rm;
1223 bits<4> Rm;
[all …]
H A DARMInstrThumb2.td524 bits<4> Rm;
534 bits<4> Rm;
544 bits<4> Rm;
583 bits<4> Rm;
596 bits<4> Rm;
610 bits<4> Rm;
622 bits<4> Rm;
634 bits<4> Rm;
676 bits<4> Rm;
2487 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
[all …]
H A DARMInstrInfo.td1813 bits<4> Rm;
1839 bits<4> Rm;
2198 bits<4> Rm;
3575 bits<4> Rm;
3589 bits<4> Rm;
3911 bits<4> Rm;
4030 bits<4> Rm;
4045 bits<4> Rm;
4202 bits<4> Rm;
4266 bits<4> Rm;
[all …]
H A DARMInstrNEON.td603 let Rm = 0b1111;
611 let Rm = 0b1111;
676 let Rm = 0b1111;
739 let Rm = 0b1111;
803 let Rm = 0b1111;
886 let Rm = 0b1111;
946 let Rm = 0b1111;
1038 let Rm = 0b1111;
1050 let Rm = 0b1111;
1148 let Rm = 0b1111;
[all …]
H A DARMInstrCDE.td85 dag Rm;
155 bits<4> Rm;
160 let Inst{15-12} = Rm{3-0};
171 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
179 let Rm = (ins GPRwithAPSR_NZCVnosp:$Rm);
190 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
476 let Rm = (ins regclass:$Vm);
484 let Rm = (ins regclass:$Qm);
498 let Iops2 = !con(IOpsPrefix, ops.Rm);
499 let Iops3 = !con(IOpsPrefix, ops.Rn, ops.Rm);
[all …]
H A DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
22 // Rd after a minimum of three cycles after the result in Rm and Rs is available
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
H A DARMInstrFormats.td802 // {11-0} imm12/Rm
820 // {11-0} imm12/Rm
841 // {11-0} imm12/Rm
895 // {3-0} imm3_0/Rm
966 bits<4> Rm;
988 bits<4> Rm;
1028 bits<4> Rm;
1044 bits<4> Rm;
1060 bits<4> Rm;
1094 bits<4> Rm;
[all …]
H A DARMInstrMVE.td485 bits<4> Rm;
487 let Inst{15-12} = Rm{3-0};
534 bits<4> Rm;
537 let Inst{15-12} = Rm{3-0};
4272 bits<4> Rm;
4285 let Inst{3-0} = Rm{3-0};
5179 bits<4> Rm;
5206 bits<4> Rm;
5803 bits<4> Rm;
6656 bits<4> Rm;
[all …]
H A DARMBaseInstrInfo.cpp3499 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
3506 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3536 if (!Rm) in getNumMicroOpsSwiftLdSt()
3538 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3548 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
3567 if (Rm == 0) in getNumMicroOpsSwiftLdSt()
3570 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
3587 if (Rm) in getNumMicroOpsSwiftLdSt()
3595 if (Rm) in getNumMicroOpsSwiftLdSt()
3613 if (Rm) in getNumMicroOpsSwiftLdSt()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td70 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
73 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
86 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
89 (LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
102 (LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
105 (LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
118 (LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
121 (LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
132 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
135 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
[all …]
H A DAArch64InstrFormats.td1761 bits<5> Rm;
2083 bits<5> Rm;
2137 bits<5> Rm;
2192 bits<5> Rm;
2267 bits<5> Rm;
2307 bits<5> Rm;
2338 bits<5> Rm;
2519 bits<5> Rm;
2544 bits<5> Rm;
2785 bits<5> Rm;
[all …]
H A DAArch64InstrInfo.td1768 def : Pat<(int_aarch64_udiv GPR32:$Rn, GPR32:$Rm), (UDIVWr GPR32:$Rn, GPR32:$Rm)>;
1769 def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>;
1770 def : Pat<(int_aarch64_sdiv GPR32:$Rn, GPR32:$Rm), (SDIVWr GPR32:$Rn, GPR32:$Rm)>;
1771 def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>;
2036 def : Pat<(int_aarch64_irg_sp i64:$Rm), (IRGstack SP, i64:$Rm)>;
2153 def : Pat<(int_aarch64_cls64 GPR64:$Rm), (EXTRACT_SUBREG (CLSXr GPR64:$Rm), sub_32)>;
4567 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
4571 def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
4882 def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>;
4885 def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>;
[all …]
H A DAArch64SchedA64FX.td2526 // [76] "ctermeq $Rn, $Rm";
2529 // [77] "ctermne $Rn, $Rm";
2864 // [189] "index $Zd, $Rn, $Rm";
2870 // [191] "index $Zd, $imm5, $Rm";
2876 // [193] "insr $Zdn, $Rm";
3553 // [420] "st1b $Zt, $Pg, [$Rn, $Rm]";
3565 // [424] "st1d $Zt, $Pg, [$Rn, $Rm]";
3873 // [531] "whilele $Pd, $Rn, $Rm";
3876 // [532] "whilelo $Pd, $Rn, $Rm";
3879 // [533] "whilels $Pd, $Rn, $Rm";
[all …]
H A DSVEInstrFormats.td1475 bits<5> Rm;
4943 bits<5> Rm;
4963 bits<5> Rm;
5010 bits<5> Rm;
5281 bits<5> Rm;
5383 bits<5> Rm;
5779 bits<5> Rm;
5801 bits<5> Rm;
5864 bits<5> Rm;
5894 bits<5> Rm;
[all …]
H A DSMEInstrFormats.td271 bits<5> Rm;
279 let Inst{20-16} = Rm;
295 gpr_ty:$Rm),
296 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
302 def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
303 …tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
448 bits<5> Rm;
456 let Inst{20-16} = Rm;
473 GPR64sp:$Rn, gpr_ty:$Rm),
474 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
H A DAArch64SchedPredicates.td232 // MOV Rd, Rm =>
233 // ORR Rd, ZR, Rm, LSL #0
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dunpredictable-MVN-arm.txt4 # MVN(S)<c> <Rd>, <Rm>{, <shift>}
8 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | imm5 |type | 0| Rm |
17 # MVN(S)<c> <Rd>, <Rm>, <type> <Rs>
21 # | cond | 0 0| 0| 1 1 1 1| S|(0)(0)(0)(0)| Rd | Rs | 0|type | 1| Rm |
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2270 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
3216 if (Rm != 0xD && Rm != 0xF && in DecodeVLDInstruction()
3590 if (Rm != 0xF) { in DecodeVLD1DupInstruction()
3602 if (Rm != 0xD && Rm != 0xF && in DecodeVLD1DupInstruction()
3643 if (Rm != 0xF) in DecodeVLD2DupInstruction()
3650 if (Rm != 0xD && Rm != 0xF) { in DecodeVLD2DupInstruction()
3675 if (Rm != 0xF) { in DecodeVLD3DupInstruction()
3684 if (Rm == 0xD) in DecodeVLD3DupInstruction()
3728 if (Rm != 0xF) { in DecodeVLD4DupInstruction()
3737 if (Rm == 0xD) in DecodeVLD4DupInstruction()
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp2133 if (Rm == 15) in EmulateBLXRm()
2142 if (Rm == 15) in EmulateBLXRm()
6592 uint32_t Rm = in EmulateLDRRegister() local
7020 uint32_t Rm = in EmulateLDRBRegister() local
7432 uint64_t Rm = in EmulateLDRHRegister() local
7836 uint64_t Rm = in EmulateLDRSBRegister() local
8264 uint64_t Rm = in EmulateLDRSHRegister() local
8395 uint64_t Rm = in EmulateSXTB() local
8480 uint64_t Rm = in EmulateSXTH() local
8565 uint64_t Rm = in EmulateUXTB() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp897 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeThreeAddrSRegInstruction() local
925 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
946 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
1499 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeAddSubERegInstruction() local
1513 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1519 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1525 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1531 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1537 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); in DecodeAddSubERegInstruction()
1877 unsigned Rm = fieldFromInstruction(insn, 16, 5); in DecodeSETMemOpInstruction() local
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Da64-ignored-fields.txt4 # The "Rm" bits are ignored, but the canonical representation has them filled
/llvm-project-15.0.7/llvm/docs/TableGen/
H A Dindex.rst240 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
243 (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
247 (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset")
251 defm : ro_signed_pats<"B", Rm, Base, Offset, Extend,
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp933 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue() local
934 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1256 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue() local
1273 uint32_t Binary = Rm; in getLdStSORegOpValue()
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A DlongMAC.ll113 ;CHECK-V7: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]
115 ;CHECK-T2-DSP: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb2-narrow-dp.ll5 // OP{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>
8 // - Rd, Rn and Rm are < r8
11 // - Rd == Rn || Rd == Rm
12 // - Rd, Rn and Rm are < r8

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