Lines Matching refs:Rm
1542 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1543 iir, opc, "\t$Rd, $Rn, $Rm",
1544 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1548 bits<4> Rm;
1554 let Inst{3-0} = Rm;
1615 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1616 iir, opc, "\t$Rd, $Rn, $Rm",
1621 bits<4> Rm;
1624 let Inst{3-0} = Rm;
1677 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1679 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1747 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1748 opc, "\t$Rn, $Rm",
1749 [(opnode GPR:$Rn, GPR:$Rm)]>,
1752 bits<4> Rm;
1759 let Inst{3-0} = Rm;
1808 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1809 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1810 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1813 bits<4> Rm;
1818 let Inst{3-0} = Rm;
1822 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1823 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1833 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1834 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1836 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1839 bits<4> Rm;
1846 let Inst{3-0} = Rm;
1850 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1851 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1877 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1878 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1879 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1884 bits<4> Rm;
1888 let Inst{3-0} = Rm;
1947 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1948 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1953 bits<4> Rm;
1956 let Inst{3-0} = Rm;
2192 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2193 "\t$Rd, $Rn, $Rm",
2194 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2198 bits<4> Rm;
2199 let Inst{3-0} = Rm;
2891 // {11-0} imm12/Rm
2909 // {11-0} imm12/Rm
2936 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2939 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2950 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2953 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2970 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2973 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2984 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2987 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3001 // {11-0} imm12/Rm
3020 // {11-0} imm12/Rm
3037 // {11-0} imm12/Rm
3056 // {11-0} imm12/Rm
3079 (ins addr_offset_none:$addr, postidx_reg:$Rm),
3081 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3082 bits<5> Rm;
3083 let Inst{23} = Rm{4};
3087 let Inst{3-0} = Rm{3-0};
3173 // {11-0} imm12/Rm
3191 // {11-0} imm12/Rm
3270 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
3273 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
3288 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
3291 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3303 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
3306 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
3319 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
3322 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
3335 // {11-0} imm12/Rm
3354 // {11-0} imm12/Rm
3376 // {11-0} imm12/Rm
3395 // {11-0} imm12/Rm
3423 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
3425 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
3426 bits<5> Rm;
3427 let Inst{23} = Rm{4};
3430 let Inst{3-0} = Rm{3-0};
3572 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
3573 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3575 bits<4> Rm;
3580 let Inst{3-0} = Rm;
3586 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3587 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3589 bits<4> Rm;
3593 let Inst{3-0} = Rm;
3697 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3698 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3729 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
3730 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3731 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot),
3733 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3775 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
3776 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3777 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
3778 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3848 def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>;
3905 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3906 string asm = "\t$Rd, $Rn, $Rm">
3911 bits<4> Rm;
3916 let Inst{3-0} = Rm;
3926 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3927 "\t$Rd, $Rm, $Rn">;
3932 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>;
3942 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm,
3945 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm,
3948 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
3951 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
3958 def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
3959 (QDADD rGPR:$Rm, rGPR:$Rn)>;
3960 def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
3961 (QDSUB rGPR:$Rm, rGPR:$Rn)>;
3963 def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
3964 (QADD8 rGPR:$Rm, rGPR:$Rn)>;
3965 def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
3966 (QSUB8 rGPR:$Rm, rGPR:$Rn)>;
3967 def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),
3968 (QADD16 rGPR:$Rm, rGPR:$Rn)>;
3969 def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn),
3970 (QSUB16 rGPR:$Rm, rGPR:$Rn)>;
3981 def : ARMV6Pat<(ARMuqadd8b rGPR:$Rm, rGPR:$Rn),
3982 (UQADD8 rGPR:$Rm, rGPR:$Rn)>;
3983 def : ARMV6Pat<(ARMuqsub8b rGPR:$Rm, rGPR:$Rn),
3984 (UQSUB8 rGPR:$Rm, rGPR:$Rn)>;
3985 def : ARMV6Pat<(ARMuqadd16b rGPR:$Rm, rGPR:$Rn),
3986 (UQADD16 rGPR:$Rm, rGPR:$Rn)>;
3987 def : ARMV6Pat<(ARMuqsub16b rGPR:$Rm, rGPR:$Rn),
3988 (UQSUB16 rGPR:$Rm, rGPR:$Rn)>;
4023 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4025 "\t$Rd, $Rn, $Rm",
4026 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
4030 bits<4> Rm;
4035 let Inst{11-8} = Rm;
4038 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4040 "\t$Rd, $Rn, $Rm, $Ra",
4041 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4045 bits<4> Rm;
4051 let Inst{11-8} = Rm;
4198 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
4199 "mvn", "\t$Rd, $Rm",
4200 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
4202 bits<4> Rm;
4207 let Inst{3-0} = Rm;
4266 bits<4> Rm;
4269 let Inst{11-8} = Rm;
4277 bits<4> Rm;
4281 let Inst{11-8} = Rm;
4289 bits<4> Rm;
4293 let Inst{11-8} = Rm;
4302 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4303 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
4304 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
4312 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
4315 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
4316 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
4322 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
4323 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
4324 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
4333 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
4335 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
4336 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
4340 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4341 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
4342 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4346 bits<4> Rm;
4351 let Inst{11-8} = Rm;
4359 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4360 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4362 (smullohi GPR:$Rn, GPR:$Rm))]>,
4367 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4368 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4370 (umullohi GPR:$Rn, GPR:$Rm))]>,
4376 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4379 (smullohi GPR:$Rn, GPR:$Rm))],
4380 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4385 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4388 (umullohi GPR:$Rn, GPR:$Rm))],
4389 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4397 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4398 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4402 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4403 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4408 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4410 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4415 bits<4> Rm;
4419 let Inst{11-8} = Rm;
4426 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4428 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4433 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4435 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4444 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4445 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
4446 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4452 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4453 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
4454 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4461 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4462 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
4463 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4468 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4469 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
4470 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4475 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4476 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4481 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4482 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
4483 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4488 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4489 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4490 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4494 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4495 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4496 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4500 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4501 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4502 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4506 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4507 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4508 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4512 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4513 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4514 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4518 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4519 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4520 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4529 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4530 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4532 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4537 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4538 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4540 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4545 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4546 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4548 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4553 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4554 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4556 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4561 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4562 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4564 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4569 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4570 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4572 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4585 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4586 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4596 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4597 (SMLALBB $Rn, $Rm, $RLo, $RHi)>;
4598 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4599 (SMLALBT $Rn, $Rm, $RLo, $RHi)>;
4600 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4601 (SMLALTB $Rn, $Rm, $RLo, $RHi)>;
4602 def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4603 (SMLALTT $Rn, $Rm, $RLo, $RHi)>;
4611 bits<4> Rm;
4615 let Inst{11-8} = Rm;
4649 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4650 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
4654 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4655 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
4659 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4661 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
4666 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4668 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
4676 def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4677 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4678 def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4679 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4680 def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4681 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4682 def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4683 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4684 def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4685 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4686 def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4687 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4688 def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4689 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4690 def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4691 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4695 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4696 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
4698 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4699 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
4706 def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm),
4707 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>;
4708 def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm),
4709 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>;
4710 def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm),
4711 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>;
4712 def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm),
4713 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>;
4718 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4719 "sdiv", "\t$Rd, $Rn, $Rm",
4720 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4724 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4725 "udiv", "\t$Rd, $Rn, $Rm",
4726 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4734 def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
4735 IIC_iUNAr, "clz", "\t$Rd, $Rm",
4736 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
4739 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4740 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
4741 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>,
4745 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4746 IIC_iUNAr, "rev", "\t$Rd, $Rm",
4747 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
4751 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4752 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
4753 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
4765 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4766 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4767 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4771 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4772 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4773 (REVSH GPR:$Rm)>;
4776 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4777 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4779 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4785 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4786 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4787 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4788 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4793 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4794 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4796 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4824 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4825 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4826 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4830 bits<4> Rm;
4842 let Inst{3-0} = Rm;
4913 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4914 "cmn", "\t$Rn, $Rm",
4916 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4918 bits<4> Rm;
4925 let Inst{3-0} = Rm;
5008 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
5010 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
6121 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
6122 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
6123 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
6124 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
6130 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
6131 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
6132 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
6133 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
6220 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
6221 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
6223 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
6224 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
6239 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
6240 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6241 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
6242 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6243 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
6244 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6245 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
6246 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6247 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
6248 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6249 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
6250 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6252 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
6253 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6254 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
6255 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6256 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
6257 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6258 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
6259 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6260 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
6261 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6262 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
6263 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
6355 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
6356 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
6357 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6359 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
6360 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
6362 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
6363 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6365 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
6366 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
6369 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
6370 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
6372 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
6373 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6375 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
6376 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6378 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
6379 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6381 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
6382 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6387 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
6388 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
6397 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
6398 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
6400 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
6401 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
6404 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6405 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6407 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6408 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6410 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6411 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6413 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6414 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,