| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 51 MVT RegisterVT = TLI.getRegisterType(Ctx, VT); in computeLegalValueVTs() local
53 ValueVTs.push_back(RegisterVT); in computeLegalValueVTs()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1090 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
1135 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1466 MVT RegisterVT; in computeRegisterProperties() local
1469 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1473 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1535 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1549 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1580 RegisterVT = getRegisterType(Context, IntermediateVT); in getVectorTypeBreakdown()
1607 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 420 Optional<MVT> RegisterVT) const override { in getNumRegisters() argument
422 if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped) in getNumRegisters()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 392 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
396 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
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| H A D | SelectionDAGBuilder.cpp | 334 MVT RegisterVT; in getCopyFromPartsVector() local
341 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
701 MVT RegisterVT; in getCopyToPartsVector() local
707 NumIntermediates, RegisterVT); in getCopyToPartsVector()
805 MVT RegisterVT = in RegsForValue() local
811 RegVTs.push_back(RegisterVT); in RegsForValue()
834 MVT RegisterVT = in getCopyFromRegs() local
855 !RegisterVT.isInteger()) in getCopyFromRegs()
917 MVT RegisterVT = in getCopyToRegs() local
1002 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands() local
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| H A D | FastISel.cpp | 1011 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1015 MyFlags.VT = RegisterVT; in lowerCallTo()
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| H A D | SelectionDAG.cpp | 2269 MVT RegisterVT; in getReducedAlign() local
2272 NumIntermediates, RegisterVT); in getReducedAlign()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1018 MVT &RegisterVT) const;
1025 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
1027 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1527 MVT RegisterVT; in getRegisterType() local
1530 NumIntermediates, RegisterVT); in getRegisterType()
1531 return RegisterVT; in getRegisterType()
1552 Optional<MVT> RegisterVT = None) const {
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 967 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
975 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
979 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
980 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
985 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
993 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
997 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
999 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
1000 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
1001 unsigned NumElements = RegisterVT.getVectorNumElements(); in analyzeFormalArgumentsCompute()
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| H A D | SIISelLowering.h | 45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | SIISelLowering.cpp | 870 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
879 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
880 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
886 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
887 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
894 RegisterVT = MVT::i16; in getVectorTypeBreakdownForCallingConv()
902 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
909 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
910 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
917 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 306 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | MipsISelLowering.cpp | 119 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
121 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
122 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
124 VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits() in getVectorTypeBreakdownForCallingConv()
126 : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits()); in getVectorTypeBreakdownForCallingConv()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 1457 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | X86ISelLowering.cpp | 2482 MVT RegisterVT; in getRegisterTypeForCallingConv() local
2484 std::tie(RegisterVT, NumRegisters) = in getRegisterTypeForCallingConv()
2486 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getRegisterTypeForCallingConv()
2487 return RegisterVT; in getRegisterTypeForCallingConv()
2513 MVT RegisterVT; in getNumRegistersForCallingConv() local
2515 std::tie(RegisterVT, NumRegisters) = in getNumRegistersForCallingConv()
2517 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE) in getNumRegistersForCallingConv()
2543 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
2550 RegisterVT = MVT::i8; in getVectorTypeBreakdownForCallingConv()
2559 RegisterVT = MVT::v32i8; in getVectorTypeBreakdownForCallingConv()
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