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Searched refs:RegisterClassHierarchy (Results 1 – 1 of 1) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp64 const CodeGenRegBank &RegisterClassHierarchy) const { in getExplicitlySpecifiedRegisterClasses()
67 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef)); in getExplicitlySpecifiedRegisterClasses()
169 const CodeGenRegBank &RegisterClassHierarchy, in visitRegisterBankClasses() argument
187 visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass, in visitRegisterBankClasses()
198 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()
213 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation() local
219 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()
251 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
277 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run() local
288 RegisterClassHierarchy, RC, "explicit", in run()
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