64       const CodeGenRegBank &RegisterClassHierarchy) const {  in getExplicitlySpecifiedRegisterClasses()
67       RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));  in getExplicitlySpecifiedRegisterClasses()
169     const CodeGenRegBank &RegisterClassHierarchy,  in visitRegisterBankClasses()  argument
181   for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {  in visitRegisterBankClasses()
187       visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,  in visitRegisterBankClasses()
197     for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {  in visitRegisterBankClasses()
198       BitVector BV(RegisterClassHierarchy.getRegClasses().size());  in visitRegisterBankClasses()
213   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();  in emitBaseClassImplementation()  local
219         (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);  in emitBaseClassImplementation()
251        << RegisterClassHierarchy.getRegClasses().size() << ");\n";  in emitBaseClassImplementation()
277   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();  in run()  local
286          Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {  in run()
288           RegisterClassHierarchy, RC, "explicit",  in run()
302   for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {  in run()