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Searched refs:RegSize (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp123 if (AArch64_AM::isLogicalImmediate(UImm, RegSize)) in splitBitmaskImm()
128 AArch64_IMM::expandMOVImm(UImm, RegSize, Insn); in splitBitmaskImm()
150 if (!AArch64_AM::isLogicalImmediate(NewImm2, RegSize)) in splitBitmaskImm()
174 if (splitBitmaskImm(Imm, RegSize, Imm0, Imm1)) in visitAND()
263 AArch64_IMM::expandMOVImm(Imm, RegSize, Insn); in splitAddSubImm()
293 if (splitAddSubImm(Imm, RegSize, Imm0, Imm1)) in visitADDSUB()
295 if (splitAddSubImm(-Imm, RegSize, Imm0, Imm1)) in visitADDSUB()
325 if (splitAddSubImm(Imm, RegSize, Imm0, Imm1)) in visitADDSSUBS()
399 unsigned RegSize = sizeof(T) * 8; in splitTwoPartImm() local
400 assert((RegSize == 32 || RegSize == 64) && in splitTwoPartImm()
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H A DAArch64FastISel.cpp1652 unsigned RegSize; in emitLogicalOp_ri() local
1663 RegSize = 32; in emitLogicalOp_ri()
1669 RegSize = 64; in emitLogicalOp_ri()
1673 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize)) in emitLogicalOp_ri()
1678 AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitLogicalOp_ri()
4034 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4081 unsigned ImmR = RegSize - Shift; in emitLSL_ri()
4137 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4185 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4253 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
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H A DAArch64FrameLowering.cpp3024 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
3027 SVECSStackSize += RegSize; in determineCalleeSaves()
3029 CSStackSize += RegSize; in determineCalleeSaves()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DInfoByHwMode.cpp119 RegSize = R->getValueAsInt("RegSize"); in RegSizeInfo()
125 return std::tie(RegSize, SpillSize, SpillAlignment) < in operator <()
126 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); in operator <()
130 return RegSize <= I.RegSize && in isSubClassOf()
136 OS << "[R=" << RegSize << ",S=" << SpillSize in writeToStream()
H A DInfoByHwMode.h147 unsigned RegSize; member
155 return std::tie(RegSize, SpillSize, SpillAlignment) ==
156 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
H A DRegisterInfoEmitter.cpp1089 uint32_t RegSize = 0; in runMCDesc() local
1091 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1095 << ", " << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1303 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFrameLowering.cpp127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
128 Size = alignTo(Size + RegSize, RegSize); in estimateStackSize()
H A DMipsCallLowering.cpp413 unsigned RegSize = 4; in lowerFormalArguments() local
415 VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize); in lowerFormalArguments()
419 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
423 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
426 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
428 LLT RegTy = LLT::scalar(RegSize * 8); in lowerFormalArguments()
431 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true); in lowerFormalArguments()
437 MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize)); in lowerFormalArguments()
H A DMipsSEFrameLowering.cpp78 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
80 unsigned MFLoOpc, unsigned RegSize);
198 unsigned RegSize) { in expandLoadACC() argument
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC() argument
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
/llvm-project-15.0.7/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp138 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
144 SmallBitVector Coverage(RegSize, false); in addMachineReg()
155 SmallBitVector CurSubReg(RegSize, false); in addMachineReg()
179 if (CurPos < RegSize) in addMachineReg()
181 -1, RegSize - CurPos, "no DWARF register encoding")); in addMachineReg()
291 unsigned RegSize = 0; in addMachineRegExpression() local
293 RegSize += Reg.SubRegSize; in addMachineRegExpression()
297 if (RegSize > FragmentInfo->SizeInBits) in addMachineRegExpression()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TileConfig.cpp179 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY() local
180 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16)) in INITIALIZE_PASS_DEPENDENCY()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h214 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate() argument
217 (RegSize != 64 && in processLogicalImmediate()
218 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) in processLogicalImmediate()
222 unsigned Size = RegSize; in processLogicalImmediate()
/llvm-project-15.0.7/clang/lib/Basic/Targets/
H A DX86.h215 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
221 HasSizeMismatch = RegSize != 32; in validateGlobalRegisterVariable()
762 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, in validateGlobalRegisterVariable() argument
768 HasSizeMismatch = RegSize != 64; in validateGlobalRegisterVariable()
773 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, in validateGlobalRegisterVariable()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp512 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
515 if (RegSize) in getRegSizeInBits()
516 return RegSize; in getRegSizeInBits()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h239 unsigned RegSize, SpillSize, SpillAlignment; member
278 return getRegClassInfo(RC).RegSize; in getRegSizeInBits()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp912 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {} in LogicOp()
914 explicit operator bool() const { return RegSize; } in operator bool()
916 unsigned RegSize = 0; member
962 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB); in convertToThreeAddress()
964 if (isRxSBGMask(Imm, And.RegSize, Start, End)) { in convertToThreeAddress()
966 if (And.RegSize == 64) { in convertToThreeAddress()
H A DSystemZFrameLowering.cpp1025 unsigned RegSize = 8; in assignCalleeSavedSpillSlots() local
1026 int FrameIdx = MFFrame.CreateFixedSpillStackObject(RegSize, Offset); in assignCalleeSavedSpillSlots()
1405 const unsigned RegSize = MF.getDataLayout().getPointerSize(); in determineFrameLayout() local
1410 MFFrame.CreateFixedSpillStackObject(RegSize, Offset - StackSize)); in determineFrameLayout()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp429 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
430 CSStackSize += RegSize; in determineCalleeSaves()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp531 int RegSize; in sizeOfSPAdjustment() local
534 RegSize = 8; in sizeOfSPAdjustment()
538 RegSize = 4; in sizeOfSPAdjustment()
551 count += RegSize; in sizeOfSPAdjustment()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DTargetInfo.h1106 unsigned RegSize, in validateGlobalRegisterVariable() argument
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp274 unsigned RegSize = Ty.getSizeInBits(); in isLoadStoreSizeLegal() local
284 if (Ty.isVector() && MemSize != RegSize) in isLoadStoreSizeLegal()
296 if (MemSize != RegSize && RegSize != 32) in isLoadStoreSizeLegal()
321 assert(RegSize >= MemSize); in isLoadStoreSizeLegal()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DTargetInfo.cpp4888 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
4890 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
4893 CGF.Int8Ty, RegAddr.getAlignment().alignmentOfArrayElement(RegSize)); in EmitVAArg()
6033 int RegSize = IsIndirect ? 8 : TySize.getQuantity(); in EmitAAPCSVAArg() local
6039 RegSize = llvm::alignTo(RegSize, 8); in EmitAAPCSVAArg()
6045 RegSize = 16 * NumRegs; in EmitAAPCSVAArg()
6086 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs"); in EmitAAPCSVAArg()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp858 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments() local
859 assert(RegSize == 32 || RegSize == 64 || in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp4537 unsigned RegSize = Ty.getSizeInBits(); in emitTST() local
4538 bool Is32Bit = (RegSize == 32); in emitTST()
4547 if (AArch64_AM::isLogicalImmediate(Imm, RegSize)) { in emitTST()
4549 TstMI.addImm(AArch64_AM::encodeLogicalImmediate(Imm, RegSize)); in emitTST()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp709 unsigned RegSize = RegTy.getSizeInBits(); in matchCombineLoadWithAndMask() local
720 if (MaskSizeBits >= RegSize) in matchCombineLoadWithAndMask()
735 else if (LoadSizeBits > MaskSizeBits || LoadSizeBits == RegSize) in matchCombineLoadWithAndMask()

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