| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVMakeCompressible.cpp | 241 if (CandidateRegImm.Reg == RegImm.Reg && in analyzeCompressibleUses()
242 CandidateRegImm.Imm == RegImm.Imm) { in analyzeCompressibleUses()
255 if (MI.modifiesRegister(RegImm.Reg, TRI)) in analyzeCompressibleUses()
272 if (RISCV::GPRRegClass.contains(RegImm.Reg)) in analyzeCompressibleUses()
344 if (!RegImm.Reg && RegImm.Imm == 0) in runOnMachineFunction()
357 assert(isInt<12>(RegImm.Imm)); in runOnMachineFunction()
359 .addReg(RegImm.Reg) in runOnMachineFunction()
360 .addImm(RegImm.Imm); in runOnMachineFunction()
366 assert(RegImm.Imm == 0); in runOnMachineFunction()
371 .addReg(RegImm.Reg) in runOnMachineFunction()
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| H A D | RISCVInstrInfo.cpp | 730 case RISCVMatInt::RegImm: in movImm()
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| H A D | RISCVISelDAGToDAG.cpp | 175 case RISCVMatInt::RegImm: in selectImmSeq()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 87 struct RegImm { struct in __anon2d0b40300111::AArch64RedundantCopyElimination
90 RegImm(MCPhysReg Reg, int32_t Imm) : Reg(Reg), Imm(Imm) {} in RegImm() argument
94 SmallVectorImpl<RegImm> &KnownRegs,
136 KnownRegs.push_back(RegImm(CondBr.getOperand(0).getReg(), 0)); in knownRegValInBlock()
203 KnownRegs.push_back(RegImm(SrcReg, KnownImm)); in knownRegValInBlock()
218 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
263 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
304 SmallVector<RegImm, 4> KnownRegs; in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
357 if (all_of(KnownRegs, [&](RegImm KnownReg) { in optimizeBlock()
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 116 : Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {} in AVROperand()
118 : Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {} in AVROperand()
120 : Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {} in AVROperand()
128 RegisterImmediate RegImm; member
200 return RegImm.Reg; in getReg()
205 return RegImm.Imm; in getImm()
234 RegImm = {RegNo, nullptr}; in makeReg()
239 RegImm = {0, Ex}; in makeImm()
244 RegImm = {RegNo, Imm}; in makeMemri()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.h | 22 RegImm, // ADDI/ADDIW/SLLI/SRLI/BSETI/BCLRI enumerator
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| H A D | RISCVMatInt.cpp | 418 return RISCVMatInt::RegImm; in getOpndKind()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 941 if (auto RegImm = isAddImmediate(MI, Reg)) { in describeLoadedValue() local
942 Register SrcReg = RegImm->Reg; in describeLoadedValue()
943 int64_t Offset = RegImm->Imm; in describeLoadedValue()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1204 } else if (auto RegImm = isAddImmediate(MI, Reg)) { in describeLoadedValue() local
1205 Register SrcReg = RegImm->Reg; in describeLoadedValue()
1206 Offset = RegImm->Imm; in describeLoadedValue()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 2327 case RISCVMatInt::RegImm: in emitLoadImm()
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