| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 30 const RegisterClassInfo &RegClassInfo, in create() argument
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
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| H A D | RegAllocEvictionAdvisor.cpp | 130 RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)), in RegAllocEvictionAdvisor()
234 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in canEvictInterferenceBasedOnCost()
235 RegClassInfo.getNumAllocatableRegs( in canEvictInterferenceBasedOnCost()
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| H A D | BreakFalseDeps.cpp | 40 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
155 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
288 RegClassInfo.runOnMachineFunction(mf); in runOnMachineFunction()
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| H A D | RegAllocBase.cpp | 65 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); in init()
128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
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| H A D | RegAllocBase.h | 70 RegisterClassInfo RegClassInfo; variable
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| H A D | RegAllocGreedy.cpp | 309 (2 * RegClassInfo.getNumAllocatableRegs(&RC)); in enqueue()
420 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in canReassign()
489 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg()
505 uint8_t MinCost = RegClassInfo.getMinCost(RC); in getOrderLimit()
515 OrderLimit = RegClassInfo.getLastCostChange(RC); in getOrderLimit()
883 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in splitAroundRegion()
1178 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); in tryBlockSplit()
1242 if (!RegClassInfo.isProperSubClass(CurRC)) in tryInstructionSplit()
1260 RegClassInfo.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1270 TII, TRI, RegClassInfo)) { in tryInstructionSplit()
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| H A D | CriticalAntiDepBreaker.h | 41 const RegisterClassInfo &RegClassInfo; variable
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| H A D | PostRASchedulerList.cpp | 78 RegisterClassInfo RegClassInfo; member in __anon3b4013580111::PostRAScheduler
287 RegClassInfo.runOnMachineFunction(Fn); in runOnMachineFunction()
310 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, in runOnMachineFunction()
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| H A D | AllocationOrder.h | 85 const RegisterClassInfo &RegClassInfo,
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| H A D | RegAllocFast.cpp | 82 RegisterClassInfo RegClassInfo; member in __anone082371b0111::RegAllocFast
799 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
852 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
983 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1225 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in allocateInstruction()
1226 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
1552 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; variable
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| H A D | RegAllocEvictionAdvisor.h | 145 const RegisterClassInfo &RegClassInfo; variable
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| H A D | MachineCombiner.cpp | 75 RegisterClassInfo RegClassInfo; member in __anonec91dd480111::MachineCombiner
601 TII->shouldReduceRegisterPressure(MBB, &RegClassInfo); in combineInstructions()
762 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | CriticalAntiDepBreaker.cpp | 44 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
406 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| H A D | RegAllocBasic.cpp | 266 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
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| H A D | MachineScheduler.cpp | 157 RegClassInfo = new RegisterClassInfo(); in MachineSchedContext()
161 delete RegClassInfo; in ~MachineSchedContext()
406 RegClassInfo->runOnMachineFunction(*MF); in runOnMachineFunction()
1017 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, in initRegPressure()
1019 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in initRegPressure()
1071 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1101 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
1284 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd, in buildDAGWithRegPressure()
2944 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( in initPolicy()
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| H A D | RegAllocGreedy.h | 145 const RegisterClassInfo &getRegClassInfo() const { return RegClassInfo; } in getRegClassInfo()
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| H A D | MLRegallocEvictAdvisor.cpp | 573 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg())) < in loadInterferenceFeatures()
574 RegClassInfo.getNumAllocatableRegs( in loadInterferenceFeatures()
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| H A D | MachineSink.cpp | 127 RegisterClassInfo RegClassInfo; member in __anon7779fb4e0111::MachineSinking
435 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
717 RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(), in getBBRegisterPressure()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 41 RegisterClassInfo RegClassInfo; member in __anon86cdcd170111::SIPreAllocateWWMRegs
103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
198 RegClassInfo.runOnMachineFunction(MF); in runOnMachineFunction()
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| H A D | SIMachineScheduler.h | 445 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 238 struct RegClassInfo { struct
250 const RegClassInfo *const RCInfos; argument
260 const RegClassInfo *const RCIs,
732 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { in getRegClassInfo()
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| H A D | MachineScheduler.h | 135 RegisterClassInfo *RegClassInfo; member
394 RegisterClassInfo *RegClassInfo;
434 RegClassInfo(C->RegClassInfo), RPTracker(RegPressure), in ScheduleDAGMILive()
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| H A D | MachinePipeliner.h | 72 RegisterClassInfo RegClassInfo; variable
122 const RegisterClassInfo &RegClassInfo; variable
205 RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI), in SwingSchedulerDAG()
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| H A D | VLIWMachineScheduler.h | 79 RegisterClassInfo *getRegClassInfo() { return RegClassInfo; } in getRegClassInfo()
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