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Searched refs:RegClassID (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp100 unsigned RegClassID; in Select() local
107 RegClassID = R600::R600_Reg64RegClassID; in Select()
111 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
113 RegClassID = R600::R600_Reg128RegClassID; in Select()
118 SelectBuildVector(N, RegClassID); in Select()
H A DAMDGPUISelDAGToDAG.h109 void SelectBuildVector(SDNode *N, unsigned RegClassID);
H A DAMDGPUISelDAGToDAG.cpp453 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
458 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
475 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
580 unsigned RegClassID = in Select() local
582 SelectBuildVector(N, RegClassID); in Select()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h108 const char* getRegClassName(unsigned RegClassID) const;
111 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
H A DAMDGPUDisassembler.cpp1042 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
1044 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1063 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
1065 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
1067 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1630 switch (RegClassID) { in GetSIDIForRegClass()
1664 int RegClassID = -1; in VerifyAndAdjustOperands() local
1685 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1686 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1692 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1694 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1696 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
1703 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()
4838 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, in parseSEHRegisterNumber() argument
4849 if (!X86MCRegisterClasses[RegClassID].contains(RegNo)) { in parseSEHRegisterNumber()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
H A DAArch64RegisterInfo.td655 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
885 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
929 # RegClassSuffix # "RegClassID>";
968 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1145 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1280 # EltSize # ", AArch64::" # RC # "RegClassID>";
1306 # EltSize # ", AArch64::" # RC # "RegClassID>";
1341 # EltSize # ", AArch64::" # RC # "RegClassID>";
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1009 unsigned RegClassID; in convertVRToVRMx() local
1011 RegClassID = RISCV::VRM2RegClassID; in convertVRToVRMx()
1013 RegClassID = RISCV::VRM4RegClassID; in convertVRToVRMx()
1015 RegClassID = RISCV::VRM8RegClassID; in convertVRToVRMx()
1019 &RISCVMCRegisterClasses[RegClassID]); in convertVRToVRMx()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp207 unsigned RegClassID; in createTuple() local
219 RegClassID = M1TupleRegClassIDs[NF - 2]; in createTuple()
225 RegClassID = M2TupleRegClassIDs[NF - 2]; in createTuple()
231 RegClassID = RISCV::VRN2M4RegClassID; in createTuple()
238 Ops.push_back(CurDAG.getTargetConstant(RegClassID, DL, MVT::i32)); in createTuple()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp76 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { in isMemOperand() argument
79 const MCRegisterClass &RC = X86MCRegisterClasses[RegClassID]; in isMemOperand()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1760 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1767 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1273 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1275 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1278 template <unsigned RegClassID, int ExtWidth>
1283 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1853 template<unsigned Bits, unsigned RegClassID>
1856 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()