| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | RegisterInfoEmitter.cpp | 63 RegBank.computeDerivedInfo(); in RegisterInfoEmitter()
224 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
880 const auto &Regs = RegBank.getRegisters(); in runMCDesc()
914 Reg.addSubRegsPreOrder(SR, RegBank); in runMCDesc()
1164 if (!RegBank.getSubRegIndices().empty()) { in runTargetHeader()
1569 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
1638 RegBank.getRegCategories(); in runTargetDesc()
1707 runEnums(OS, Target, RegBank); in run()
1710 runMCDesc(OS, Target, RegBank); in run()
1713 runTargetHeader(OS, Target, RegBank); in run()
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| H A D | CodeGenRegisters.cpp | 187 CodeGenRegister *Reg = RegBank.getReg(Alias); in buildObjectGraph()
442 RegUnits.set(RegBank.newRegUnit(this)); in computeSubRegs()
553 SubReg.second->computeSuperRegs(RegBank); in computeSuperRegs()
570 TopoSig = RegBank.getTopoSig(Id); in computeSuperRegs()
580 SR->addSubRegsPreOrder(OSet, RegBank); in addSubRegsPreOrder()
974 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()
1020 RC.inheritProperties(RegBank); in computeSubClasses()
1037 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()
1785 if (Reg->inheritRegUnits(RegBank)) in normalizeWeight()
1786 computeUberWeights(UberSets, RegBank); in normalizeWeight()
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| H A D | CodeGenTarget.h | 52 mutable std::unique_ptr<CodeGenRegBank> RegBank; variable
112 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
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| H A D | CodeGenRegisters.h | 250 bool inheritRegUnits(CodeGenRegBank &RegBank);
257 unsigned getWeight(const CodeGenRegBank &RegBank) const;
394 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
445 void buildRegUnitSet(const CodeGenRegBank &RegBank,
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| H A D | CodeGenTarget.cpp | 302 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()
356 if (!RegBank) in getRegBank()
357 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); in getRegBank()
358 return *RegBank; in getRegBank()
363 CodeGenRegBank &RegBank, in getSuperRegForSubReg() argument
367 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegisterBankInfo.cpp | 69 const RegisterBank &RegBank = getRegBank(Idx); in verify() local
70 assert(Idx == RegBank.getID() && in verify()
124 assert(RegBank.covers(*RC) && in getRegBankFromConstraints()
126 return &RegBank; in getRegBankFromConstraints()
266 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0); in hashPartialMapping()
273 PartMapping.RegBank); in hash_value()
516 assert(RegBank && "Register bank not set"); in verify()
526 if (RegBank) in print()
527 OS << *RegBank; in print()
538 if (Part->Length != First->Length || Part->RegBank != First->RegBank) in partsAllUniform()
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| H A D | MachineRegisterInfo.cpp | 62 const RegisterBank &RegBank) { in setRegBank() argument
63 VRegInfo[Reg].first = &RegBank; in setRegBank()
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| H A D | MachineVerifier.cpp | 2078 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg); in visitMachineOperand() local
2081 if (!RegBank && isFunctionRegBankSelected) { in visitMachineOperand()
2089 if (RegBank && Ty.isValid() && in visitMachineOperand()
2090 RegBank->getSize() < Ty.getSizeInBits()) { in visitMachineOperand()
2093 errs() << "Register bank " << RegBank->getName() << " too small(" in visitMachineOperand()
2094 << RegBank->getSize() << ") to fit " << Ty.getSizeInBits() in visitMachineOperand()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RegisterBankInfo.h | 60 const RegisterBank *RegBank; member
66 const RegisterBank &RegBank) in PartialMapping()
67 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {} in PartialMapping()
463 const RegisterBank &RegBank) const;
471 const RegisterBank &RegBank) const;
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| H A D | RegisterBank.h | 92 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
93 RegBank.print(OS);
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| H A D | MachineRegisterInfo.h | 684 void setRegBank(Register Reg, const RegisterBank &RegBank);
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 138 unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass() local
190 assert(RegBank && "Can't get reg bank for virtual register"); in guessRegClass()
193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
356 unsigned RegBank, in selectLoadStoreOpCode() argument
360 if (RegBank == ARM::GPRRegBankID) { in selectLoadStoreOpCode()
374 if (RegBank == ARM::FPRRegBankID) { in selectLoadStoreOpCode()
1087 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID(); in select() local
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| H A D | ARMRegisterBankInfo.cpp | 52 PM.RegBank->getID() == RegBankID; in checkPartMapping()
478 (Mapping.RegBank->getID() != ARM::FPRRegBankID || in getInstrMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 263 ValMapping.BreakDown[0].RegBank == ValMapping.BreakDown[1].RegBank); in getBreakDownCost()
1342 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank; in applyMappingSBufferLoad()
1904 const RegisterBank &RegBank, in extendLow32IntoHigh32() argument
1916 B.getMRI()->setRegBank(ShiftAmt.getReg(0), RegBank); in extendLow32IntoHigh32()
2698 const RegisterBank *DstBank = DstMapping.BreakDown[0].RegBank; in applyMappingImpl()
3312 unsigned RegBank = AMDGPU::InvalidRegBankID; in getMappingType() local
3319 RegBank = regBankUnion(RegBank, Bank->getID()); in getMappingType()
3320 if (RegBank == AMDGPU::VGPRRegBankID) in getMappingType()
3325 return RegBank; in getMappingType()
4202 unsigned RSrcBank = OpdsMapping[1]->BreakDown[0].RegBank->getID(); in getInstrMapping()
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| H A D | AMDGPUGenRegisterBankInfo.def | 46 // StartIdx, Length, RegBank
196 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());
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| H A D | VOP3Instructions.td | 457 const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
458 if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
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| /llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 597 Info.D.RegBank = nullptr; in parseRegisterInfo()
604 const RegisterBank *RegBank = Target->getRegBank(VReg.Class.Value); in parseRegisterInfo() local
605 if (!RegBank) in parseRegisterInfo()
611 Info.D.RegBank = RegBank; in parseRegisterInfo()
680 MRI.setRegBank(Reg, *Info.D.RegBank); in setupRegisterInfo()
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| H A D | MIParser.cpp | 295 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks() local
297 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank)); in initNames2RegBanks()
1517 const RegisterBank *RegBank = nullptr; in parseRegisterClassOrBank() local
1519 RegBank = PFS.Target.getRegBank(Name); in parseRegisterClassOrBank()
1520 if (!RegBank) in parseRegisterClassOrBank()
1530 RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC; in parseRegisterClassOrBank()
1531 if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank) in parseRegisterClassOrBank()
1533 RegInfo.D.RegBank = RegBank; in parseRegisterClassOrBank()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
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| H A D | X86InstructionSelector.cpp | 202 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass() local
203 return getRegClass(Ty, RegBank); in getRegClass()
1325 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues() local
1329 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1335 MRI.setRegBank(Tmp, RegBank); in selectMergeValues()
1394 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in materializeFP() local
1399 getLoadStoreOp(DstTy, RegBank, TargetOpcode::G_LOAD, Alignment); in materializeFP()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64GenRegisterBankInfo.def | 15 /* StartIdx, Length, RegBank */
131 Map.RegBank == &RB;
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 44 const RegisterBank *RegBank; member
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 121 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in assignmentMatch()
262 const RegisterBank *DesiredRegBank = ValMapping.BreakDown[0].RegBank; in getRepairCost()
603 MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank); in applyMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 750 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[0]].RegBank, in getInstrMapping()
751 *AArch64GenRegisterBankInfo::PartMappings[OpRegBankIdx[1]].RegBank, in getInstrMapping()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.h | 167 void setRegBank(Register Reg, const RegisterBank *RegBank);
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