62     CodeGenRegBank &RegBank = Target.getRegBank();  in RegisterInfoEmitter()  local
63     RegBank.computeDerivedInfo();  in RegisterInfoEmitter()
91   void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
93   void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
95   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,  in EmitRegUnitPressure()  argument
210   unsigned NumRCs = RegBank.getRegClasses().size();  in EmitRegUnitPressure()
211   unsigned NumSets = RegBank.getNumRegPressureSets();  in EmitRegUnitPressure()
217   for (const auto &RC : RegBank.getRegClasses()) {  in EmitRegUnitPressure()
219     OS << "    {" << RC.getWeight(RegBank) << ", ";  in EmitRegUnitPressure()
224       RC.buildRegUnitSet(RegBank, RegUnits);  in EmitRegUnitPressure()
225       OS << RegBank.getRegUnitSetWeight(RegUnits);  in EmitRegUnitPressure()
236   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
238     if (RegBank.getRegUnit(UnitIdx).Weight > 1)  in EmitRegUnitPressure()
244      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
248     for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
250       const RegUnit &RU = RegBank.getRegUnit(UnitIdx);  in EmitRegUnitPressure()
274     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
290     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
302   unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();  in EmitRegUnitPressure()
306     ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);  in EmitRegUnitPressure()
309       PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);  in EmitRegUnitPressure()
341      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
345   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
347     OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])  in EmitRegUnitPressure()
697                                               CodeGenRegBank &RegBank,  in emitComposeSubRegIndices()  argument
699   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndices()
767                                                     CodeGenRegBank &RegBank,  in emitComposeSubRegIndexLaneMask()  argument
770   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndexLaneMask()
874                                CodeGenRegBank &RegBank) {  in runMCDesc()  argument
880   const auto &Regs = RegBank.getRegisters();  in runMCDesc()
882   auto &SubRegIndices = RegBank.getSubRegIndices();  in runMCDesc()
914     Reg.addSubRegsPreOrder(SR, RegBank);  in runMCDesc()
1027   for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {  in runMCDesc()
1028     ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();  in runMCDesc()
1039   const auto &RegisterClasses = RegBank.getRegClasses();  in runMCDesc()
1128      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "  in runMCDesc()
1145                                      CodeGenRegBank &RegBank) {  in runTargetHeader()  argument
1164   if (!RegBank.getSubRegIndices().empty()) {  in runTargetHeader()
1198   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetHeader()
1221                                    CodeGenRegBank &RegBank){  in runTargetDesc()  argument
1234   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetDesc()
1235   const auto &SubRegIndices = RegBank.getSubRegIndices();  in runTargetDesc()
1456   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()
1509     emitComposeSubRegIndices(OS, RegBank, ClassName);  in runTargetDesc()
1510     emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);  in runTargetDesc()
1545   EmitRegUnitPressure(OS, RegBank, ClassName);  in runTargetDesc()
1569   printMask(OS, RegBank.CoveringLanes);  in runTargetDesc()
1575      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"  in runTargetDesc()
1594     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()
1605     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()
1612       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());  in runTargetDesc()
1613       Covered |= RegBank.computeCoveredRegisters(  in runTargetDesc()
1638       RegBank.getRegCategories();  in runTargetDesc()
1705   CodeGenRegBank &RegBank = Target.getRegBank();  in run()  local
1707   runEnums(OS, Target, RegBank);  in run()
1710   runMCDesc(OS, Target, RegBank);  in run()
1713   runTargetHeader(OS, Target, RegBank);  in run()
1716   runTargetDesc(OS, Target, RegBank);  in run()
1723   CodeGenRegBank &RegBank = Target.getRegBank();  in debugDump()  local
1732   for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) {  in debugDump()
1753     for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) {  in debugDump()
1766   for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) {  in debugDump()
1772   for (const CodeGenRegister &R : RegBank.getRegisters()) {  in debugDump()