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Searched refs:Reg2 (Results 1 – 25 of 40) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNVOPDUtils.cpp69 Register Dst, Reg0, Reg1, Reg2; in checkVOPDRegConstraints() member
79 Comp.Reg2 = Comp.MI.getOperand(3).getReg(); in checkVOPDRegConstraints()
90 Comp.Reg2 = Comp.MI.getOperand(0).getReg(); in checkVOPDRegConstraints()
132 if (CInfo[0].Reg2 && CInfo[1].Reg2 && in checkVOPDRegConstraints()
133 !((CInfo[0].Reg2 ^ CInfo[1].Reg2) & 0x1)) in checkVOPDRegConstraints()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp658 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
660 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
663 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
666 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
669 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
672 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
677 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
683 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
686 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
689 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 && in generateCompactUnwindEncoding()
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/llvm/
H A Dprefer-register-over-unsigned.cpp32 unsigned Reg2 = getReg(); in apply_2() local
59 Register Reg2 = getReg(); in done_2() local
81 unsigned Reg2 = getRegLike(); in do_nothing_2() local
H A Dprefer-register-over-unsigned3.cpp21 unsigned Reg2 = getReg(); in do_nothing_2() local
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/
H A DTargetTest.cpp108 const unsigned Reg2 = Mips::T2_64; in TEST_F() local
109 EXPECT_THAT(setRegTo(Reg2, APInt(32, Value2)), in TEST_F()
110 ElementsAre(IsLoadLow16BitImm(Reg2, 0xFFFFU, false), in TEST_F()
111 IsShift(Reg2, 16, false))); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp875 unsigned Reg2) { in EmitInstrRegReg() argument
884 Reg1 = Reg2; in EmitInstrRegReg()
885 Reg2 = Temp; in EmitInstrRegReg()
889 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
895 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
899 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
906 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
910 Reg1 = Reg2; in EmitMovFPIntPair()
911 Reg2 = temp; in EmitMovFPIntPair()
914 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
H A DMips16InstrInfo.h120 unsigned Reg1, unsigned Reg2) const;
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
293 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
H A DMipsTargetStreamer.h134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dnewvaluejump2.ll10 %Reg2 = alloca i32, align 4
11 %0 = load i32, i32* %Reg2, align 4
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp1113 Register Reg1, Reg2; in parseAddress() local
1159 if (parseAddressRegister(Reg2)) in parseAddress()
1161 Base = Regs[Reg2.Num]; in parseAddress()
1167 if (parseAddressRegister(Reg2)) in parseAddress()
1169 Base = Regs[Reg2.Num]; in parseAddress()
1191 if (parseAddressRegister(Reg2)) in parseAddress()
1193 Base = Regs[Reg2.Num]; in parseAddress()
1205 if (parseAddressRegister(Reg2)) in parseAddress()
1207 Base = Regs[Reg2.Num]; in parseAddress()
1501 Register Reg1, Reg2; in parseOperand() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2441 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
2445 if (Reg2 == Reg1 + 1) in invalidateWindowsRegisterPairing()
2572 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2578 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
2717 MIB.addReg(RPI.Reg2); in spillCalleeSavedRegisters()
2729 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
2785 std::swap(Reg1, Reg2); in spillCalleeSavedRegisters()
2793 MBB.addLiveIn(Reg2); in spillCalleeSavedRegisters()
2794 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2)); in spillCalleeSavedRegisters()
2835 unsigned Reg2 = RPI.Reg2; in restoreCalleeSavedRegisters() local
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp199 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
202 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitStore()
212 MIB.addReg(Reg2) in emitStore()
222 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
225 assert(!(IsFloat ^ AArch64::FPR64RegClass.contains(Reg2))); in emitLoad()
235 MIB.addReg(Reg2, getDefRegState(true)) in emitLoad()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegReAssign.cpp81 const MCPhysReg Reg2 = *BC.MRI->getLLVMRegNum(CFIReg2, /*isEH=*/false); in swap() local
82 if (AliasA.test(Reg2)) { in swap()
87 BC.MIB->getAliasSized(B, BC.MIB->getRegSize(Reg2)), in swap()
89 } else if (AliasB.test(Reg2)) { in swap()
94 BC.MIB->getAliasSized(A, BC.MIB->getRegSize(Reg2)), in swap()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
/llvm-project-15.0.7/llvm/unittests/DebugInfo/DWARF/
H A DDWARFDebugFrameTest.cpp998 constexpr uint8_t Reg2 = 15; in TEST() local
1004 Reg2, 2, dwarf::DW_CFA_offset_extended_sf, Reg3, Neg1SLEB}), in TEST()
1013 Reg2, dwarf::UnwindLocation::createAtCFAPlusOffset(-16)); in TEST()
1054 constexpr uint8_t Reg2 = 15; in TEST() local
1058 dwarf::DW_CFA_val_offset_sf, Reg2, Neg1SLEB}), in TEST()
1067 Reg2, dwarf::UnwindLocation::createIsCFAPlusOffset(8)); in TEST()
1167 constexpr uint8_t Reg2 = 15; in TEST() local
1172 dwarf::DW_CFA_remember_state, dwarf::DW_CFA_offset | Reg2, 2, in TEST()
1189 Reg2, dwarf::UnwindLocation::createAtCFAPlusOffset(-16)); in TEST()
1195 Reg2, dwarf::UnwindLocation::createAtCFAPlusOffset(-16)); in TEST()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h166 unsigned Reg2, bool isKill2) { in addRegReg() argument
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DTargetInstrInfo.cpp184 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
199 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2) in commuteInstructionImpl()
207 Reg0 = Reg2; in commuteInstructionImpl()
209 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
230 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
243 if (Register::isPhysicalRegister(Reg2)) in commuteInstructionImpl()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp83 unsigned Reg2);
446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
454 .addReg(Reg2) in createRegSequence()
H A DThumb2SizeReduction.cpp761 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
764 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
766 if (Reg0 != Reg2) { in ReduceTo2Addr()
796 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
797 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h103 bool contains(Register Reg1, Register Reg2) const { in contains() argument
106 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
108 return MC->contains(Reg1.asMCReg(), Reg2.asMCReg()); in contains()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp280 unsigned Reg2 = in getRegisterSeqOpValue() local
283 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1); in getRegisterSeqOpValue()

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