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Searched refs:Reg1 (Results 1 – 25 of 50) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNVOPDUtils.cpp69 Register Dst, Reg0, Reg1, Reg2; in checkVOPDRegConstraints() member
84 Comp.Reg1 = Comp.MI.getOperand(2).getReg(); in checkVOPDRegConstraints()
89 Comp.Reg1 = Comp.MI.getOperand(2).getReg(); in checkVOPDRegConstraints()
94 Comp.Reg1 = Comp.MI.getOperand(2).getReg(); in checkVOPDRegConstraints()
99 Comp.Reg1 = Comp.MI.getOperand(2).getReg(); in checkVOPDRegConstraints()
128 if (CInfo[0].Reg1 && CInfo[1].Reg1 && in checkVOPDRegConstraints()
129 CInfo[0].Reg1 % NumVGPRBanks == CInfo[1].Reg1 % NumVGPRBanks) in checkVOPDRegConstraints()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/
H A DTargetTest.cpp91 const unsigned Reg1 = Mips::T1; in TEST_F() local
92 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)), in TEST_F()
93 ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true), in TEST_F()
94 IsLoadLow16BitImm(Reg1, 0xFFFFU, true))); in TEST_F()
103 const unsigned Reg1 = Mips::T1_64; in TEST_F() local
104 EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)), in TEST_F()
105 ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false), in TEST_F()
106 IsLoadLow16BitImm(Reg1, 0xFFFFU, false))); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp657 Reg1 = getXRegFromWReg(Reg1); in generateCompactUnwindEncoding()
660 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
663 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
666 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
669 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
672 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
676 Reg1 = getDRegFromBReg(Reg1); in generateCompactUnwindEncoding()
683 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
686 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
689 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 && in generateCompactUnwindEncoding()
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/llvm/
H A Dprefer-register-over-unsigned.cpp24 unsigned Reg1 = getReg(); in apply_1() local
52 llvm::Register Reg1 = getReg(); in done_1() local
74 unsigned Reg1 = getRegLike(); in do_nothing_1() local
H A Dprefer-register-over-unsigned3.cpp14 unsigned Reg1 = getReg(); in do_nothing_1() local
/llvm-project-15.0.7/llvm/unittests/DebugInfo/DWARF/
H A DDWARFDebugFrameTest.cpp997 constexpr uint8_t Reg1 = 14; in TEST() local
1011 Reg1, dwarf::UnwindLocation::createAtCFAPlusOffset(-8)); in TEST()
1053 constexpr uint8_t Reg1 = 14; in TEST() local
1057 parseCFI(TestFDE, {dwarf::DW_CFA_val_offset, Reg1, 1, in TEST()
1065 Reg1, dwarf::UnwindLocation::createIsCFAPlusOffset(-8)); in TEST()
1103 constexpr uint8_t Reg1 = 14; in TEST() local
1112 Reg1, dwarf::UnwindLocation::createAtCFAPlusOffset(-8)); in TEST()
1166 constexpr uint8_t Reg1 = 14; in TEST() local
1246 constexpr uint8_t Reg1 = 14; in TEST() local
1253 VerifyLocs.setRegisterLocation(Reg1, in TEST()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1002 .addImm(Reg1) in InsertSEH()
1053 .addImm(Reg1) in InsertSEH()
2445 if (Reg2 == Reg1 + 1) in invalidateWindowsRegisterPairing()
2452 if (Reg1 >= AArch64::X19 && Reg1 <= AArch64::X27 && in invalidateWindowsRegisterPairing()
2716 MIB.addReg(RPI.Reg1); in spillCalleeSavedRegisters()
2728 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
2785 std::swap(Reg1, Reg2); in spillCalleeSavedRegisters()
2790 MBB.addLiveIn(Reg1); in spillCalleeSavedRegisters()
2799 MIB.addReg(Reg1, getPrologueDeath(MF, Reg1)) in spillCalleeSavedRegisters()
2834 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp199 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore() argument
201 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitStore()
213 .addReg(Reg1) in emitStore()
222 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad() argument
224 bool IsFloat = AArch64::FPR64RegClass.contains(Reg1); in emitLoad()
236 .addReg(Reg1, getDefRegState(true)) in emitLoad()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h130 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
132 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
134 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
138 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
140 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsAsmPrinter.h94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
H A DMipsAsmPrinter.cpp874 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg() argument
883 unsigned Temp = Reg1; in EmitInstrRegReg()
884 Reg1 = Reg2; in EmitInstrRegReg()
888 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegReg()
894 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg() argument
898 I.addOperand(MCOperand::createReg(Reg1)); in EmitInstrRegRegReg()
905 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
909 unsigned temp = Reg1; in EmitMovFPIntPair()
910 Reg1 = Reg2; in EmitMovFPIntPair()
913 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
H A DMips16InstrInfo.cpp278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig() argument
287 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); in adjustStackPtrBig()
291 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); in adjustStackPtrBig()
292 MIB3.addReg(Reg1); in adjustStackPtrBig()
296 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
387 if (Registers[i] == Reg1) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
H A DMipsSEFrameLowering.cpp464 unsigned Reg1 = in emitPrologue() local
468 std::swap(Reg0, Reg1); in emitPrologue()
476 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
481 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
484 std::swap(Reg0, Reg1); in emitPrologue()
492 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); in emitPrologue()
H A DMips16InstrInfo.h120 unsigned Reg1, unsigned Reg2) const;
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp1040 if (parseRegister(Reg1)) in parseAddress()
1113 Register Reg1, Reg2; in parseAddress() local
1135 if (parseAddressRegister(Reg1)) in parseAddress()
1137 Base = Regs[Reg1.Num]; in parseAddress()
1148 if (parseAddressRegister(Reg1)) in parseAddress()
1153 Index = Regs[Reg1.Num]; in parseAddress()
1155 Base = Regs[Reg1.Num]; in parseAddress()
1198 if (!HaveReg1 || Reg1.Group != RegV) { in parseAddress()
1501 Register Reg1, Reg2; in parseOperand() local
1510 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV in parseOperand()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h78 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
79 return contains(Reg1) && contains(Reg2); in contains()
756 uint16_t Reg1 = 0; variable
764 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
780 Reg0 = Reg1;
781 Reg1 = 0;
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
220 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
226 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
229 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
238 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
245 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
248 emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI); in emitRRI()
252 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII() argument
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h165 unsigned Reg1, bool isKill1, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp284 Register Reg1 = Op1.getReg(); in legalizeCustom() local
289 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
295 Op1.setReg(convertPtrToInt(Reg1, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp224 Register Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
248 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
263 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, in tryInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp278 unsigned Reg1 = in getRegisterSeqOpValue() local
283 unsigned Binary = ((Reg1 & 0x1f) << 5) | (Reg2 - Reg1); in getRegisterSeqOpValue()
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DPatternMatchTest.cpp292 Register Reg1; in TEST_F() local
294 m_GICmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1))); in TEST_F()
298 EXPECT_EQ(Copies[1], Reg1); in TEST_F()
317 Register Reg1; in TEST_F() local
319 m_GFCmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1))); in TEST_F()
323 EXPECT_EQ(Copies[1], Reg1); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp190 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in selectInlineAsm() local
214 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in selectInlineAsm()
229 CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32, T0.getValue(1)); in selectInlineAsm()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.h105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);

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