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Searched refs:RIP (Results 1 – 25 of 30) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td188 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
425 // RIP isn't really a register and it can't be used anywhere except in an
428 // tests because of the inclusion of RIP in this register class.
431 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
466 RIP, RSP)>;
489 // GR64_NOSP - GR64 registers except RSP (and RIP).
490 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
504 // In such cases, it is fine to use RIP as we are sure the 32 high
505 // bits are not set. We do not need variants for NOSP as RIP is not
507 // RIP is not spilled anywhere for now, so stick to 32-bit alignment
[all …]
H A DX86RegisterInfo.cpp49 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
52 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
552 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs()
695 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
906 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
H A DX86SpeculativeExecutionSideEffectSuppression.cpp83 if (MO.isReg() && X86::RIP != MO.getReg()) in hasConstantAddressingMode()
H A DX86SpeculativeLoadHardening.cpp1124 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1164 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1344 if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP && in tracePredStateThroughBlocksAndHarden()
1598 } else if (BaseMO.getReg() == X86::RIP || in hardenLoadAddr()
1610 << (BaseMO.getReg() == X86::RIP ? "RIP-relative" : "no-base") in hardenLoadAddr()
2133 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
2175 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
H A DX86AsmPrinter.cpp296 BaseReg.getReg() == X86::RIP) in PrintLeaMemReference()
394 BaseReg.getReg() == X86::RIP) in PrintIntelMemReference()
H A DX86FastISel.cpp751 AM.Base.Reg = X86::RIP; in handleConstantAddresses()
785 StubAM.Base.Reg = X86::RIP; in handleConstantAddresses()
1072 AM.Base.Reg = X86::RIP; in X86SelectCallAddress()
3490 MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0); in fastLowerCall()
3762 PICBase = X86::RIP; in X86MaterializeFP()
H A DX86ExpandPseudo.cpp108 .addReg(X86::RIP) in INITIALIZE_PASS()
H A DX86InstructionSelector.cpp620 AM.Base.Reg = X86::RIP; in selectGlobalValue()
1435 PICBase = X86::RIP; in materializeFP()
H A DX86FrameLowering.cpp1528 .addUse(X86::RIP) in emitPrologue()
2767 .addReg(X86::RIP) in emitCatchRetReturnValue()
3110 .addReg(X86::RIP) in adjustForSegmentedStacks()
H A DX86InstrInfo.cpp874 if (BaseReg == 0 || BaseReg == X86::RIP) in isReallyTriviallyReMaterializable()
4794 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1) in expandLoadStackGuard()
6693 PICBase = X86::RIP; in foldMemoryOperandImpl()
9291 .addReg(X86::RIP) in runOnMachineFunction()
9306 .addReg(X86::RIP) in runOnMachineFunction()
9624 if (MI.readsRegister(X86::RIP, &RI) || in getOutliningType()
9625 MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) || in getOutliningType()
9626 MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP)) in getOutliningType()
H A DX86MCInstLower.cpp1034 .addReg(X86::RIP) in LowerTlsAddr()
1050 .addReg(X86::RIP) in LowerTlsAddr()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DRegionPrinter.cpp134 static RegionInfo *getGraph(RegionInfoPass *RIP) { in getGraph()
135 return &RIP->getRegionInfo(); in getGraph()
/llvm-project-15.0.7/lld/test/ELF/
H A Deh-frame-merge.s34 # EH-NEXT: 0x[[#%x,]]: CFA=RSP+8: RIP=[CFA-8]
/llvm-project-15.0.7/polly/lib/Support/
H A DScopHelper.cpp213 RegionInfoPass *RIP = P->getAnalysisIfAvailable<RegionInfoPass>(); in splitEntryBlockForAlloca() local
214 RegionInfo *RI = RIP ? &RIP->getRegionInfo() : nullptr; in splitEntryBlockForAlloca()
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1299 !(BaseReg == X86::RIP || BaseReg == X86::EIP || in CheckBaseRegAndIndexRegAndScale()
1320 IndexReg == X86::EIP || IndexReg == X86::RIP || in CheckBaseRegAndIndexRegAndScale()
1402 if (RegNo == X86::RIZ || RegNo == X86::RIP || in MatchRegisterByName()
2533 if (RegNo == X86::RIP) in parseIntelOperand()
2588 if (IndexReg && BaseReg == X86::RIP) in parseIntelOperand()
2642 DefaultBaseReg = X86::RIP; in parseIntelOperand()
2648 DefaultBaseReg = X86::RIP; in parseIntelOperand()
2654 DefaultBaseReg = X86::RIP; in parseIntelOperand()
2723 if (Reg == X86::RIP) in parseATTOperand()
3008 if (BaseReg == X86::RIP) in ParseMemOperand()
[all …]
H A DX86Operand.h335 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem()
/llvm-project-15.0.7/llvm/lib/Transforms/ObjCARC/
H A DObjCARCOpts.cpp1930 for (Instruction *RIP : NewRetainReleaseRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1931 if (ReleasesToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1934 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
1987 for (Instruction *RIP : NewReleaseRetainRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1988 if (RetainsToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1991 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp622 if (Operand.isReg() && Operand.getReg() == X86::RIP) in hasPCRelOperand()
734 if ((BaseRegNum != X86::RIP && BaseRegNum != X86::NoRegister) || in evaluateMemOperandTarget()
740 if (BaseRegNum == X86::RIP) { in evaluateMemOperandTarget()
1789 MCOperand::createReg(X86::RIP)); // BaseReg in convertCallToIndirectCall()
2306 if (!DispExpr && BaseReg != X86::RIP && BaseReg != X86::RBP && in analyzeVirtualMethodCall()
2324 if (MethodRegNum == X86::RIP || MethodRegNum == X86::RBP) { in analyzeVirtualMethodCall()
2338 if (!DispExpr && Scale == 1 && BaseReg != X86::RIP && in analyzeVirtualMethodCall()
2341 BaseReg != X86::RIP) { in analyzeVirtualMethodCall()
2484 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg in createIncMemory()
3712 Inst.addOperand(MCOperand::createReg(X86::RIP)); // BaseReg in createMove()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsjlj-eh.ll99 ; UFC.__jbuf[1] = $RIP
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp410 ? X86::RIP // Should have dwarf #16. in createX86MCRegisterInfo()
459 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; in createX86MCAsmInfo()
658 if (BaseReg.getReg() == X86::RIP) in evaluateMemoryOperandAddress()
680 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() != 0 || in getMemoryOperandRelocationOffset()
H A DX86AsmBackend.cpp267 return (BaseReg == X86::RIP); in isRIPRelative()
H A DX86MCCodeEmitter.cpp334 if (BaseReg == X86::RIP || in emitMemModRMByte()
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h412 ENTRY(RIP)
/llvm-project-15.0.7/llvm/docs/TableGen/
H A Dindex.rst72 RDX, RIP, RSI, RSP, SI, SIL, SP, SPL, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
/llvm-project-15.0.7/llvm/docs/
H A DSymbolizerMarkupFormat.rst300 … CS: 0 RIP: 0x6ee17076fb80 EFL: 0x10246 CR2: 0

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