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Searched refs:RH (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
18 store i64 %tmp2122, i64* %RH
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
37 store i64 %tmp2122, i64* %RH
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmisched-fusion-addr.ll30 ; CHECK: adrp [[RH:x[0-9]+]], var_16bit
31 ; CHECK-NEXT: strh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit]
43 ; CHECK: adrp [[RH:x[0-9]+]], var_16bit
44 ; CHECK-NEXT: ldrh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit]
84 ; CHECK: adrp [[RH:x[0-9]+]], var_half
85 ; CHECK-NEXT: ldr {{h[0-9]+}}, [[[RH]], {{#?}}:lo12:var_half]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp510 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_Select() local
514 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_Select()
545 Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH); in SplitRes_Select()
554 Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH, EVLHi); in SplitRes_Select()
559 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
562 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
567 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
H A DTargetLowering.cpp6958 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL_LOHI()
7020 if (!LH.getNode() && !RH.getNode() && in expandMUL_LOHI()
7025 RH = DAG.getNode(ISD::SRL, dl, VT, RHS, Shift); in expandMUL_LOHI()
7026 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH); in expandMUL_LOHI()
7038 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH); in expandMUL_LOHI()
7040 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH); in expandMUL_LOHI()
7055 if (!MakeMUL_LOHI(LL, RH, Lo, Hi, false)) in expandMUL_LOHI()
7081 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI)) in expandMUL_LOHI()
7100 Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT); in expandMUL_LOHI()
7112 SDValue RH) const { in expandMUL()
[all …]
H A DLegalizeIntegerTypes.cpp3636 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
3638 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_Logical()
3640 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); in ExpandIntRes_Logical()
3649 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
3651 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_MUL()
3655 LL, LH, RL, RH)) in ExpandIntRes_MUL()
3706 DAG.getNode(ISD::MUL, dl, NVT, RH, LL), in ExpandIntRes_MUL()
3799 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
3801 GetExpandedInteger(RHS, RL, RH); in ExpandIntRes_MULFIX()
3807 LL, LH, RL, RH)) { in ExpandIntRes_MULFIX()
H A DLegalizeVectorTypes.cpp2108 SDValue LL, LH, RL, RH; in SplitVecRes_SETCC() local
2117 GetSplitVector(N->getOperand(1), RL, RH); in SplitVecRes_SETCC()
2119 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1); in SplitVecRes_SETCC()
2123 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2)); in SplitVecRes_SETCC()
2132 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2), MaskHi, in SplitVecRes_SETCC()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1734 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2); in propagateRegCopy() local
1736 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); in propagateRegCopy()
1789 unsigned B, RegHalf &RH);
1832 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf() argument
1899 RH.Reg = Reg; in matchHalf()
1900 RH.Sub = Sub; in matchHalf()
1901 RH.Low = Low; in matchHalf()
1903 if (!HBS::getFinalVRegClass(RH, MRI)) in matchHalf()
1904 RH.Sub = 0; in matchHalf()
H A DHexagonConstPropagation.cpp1862 bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
2516 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, in evaluateHexRSEQ32() argument
2518 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg)); in evaluateHexRSEQ32()
2520 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH)) in evaluateHexRSEQ32()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp673 SDValue LH, RH; in TryExpandADDWithMul() local
676 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
682 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); in TryExpandADDWithMul()
684 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); in TryExpandADDWithMul()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleR52.td300 "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T",
497 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
H A DARMScheduleSwift.td368 "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>;
498 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLowerMatrixIntrinsics.cpp1235 Value *RH = Builder.CreateExtractElement( in emitMatrixMultiply() local
1238 Value *Splat = Builder.CreateVectorSplat(BlockSize, RH, "splat"); in emitMatrixMultiply()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4671 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4685 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A Dfile-header-machine-types.test67 # RUN: llvm-readelf --file-headers %t.rh32.o | FileCheck %s -DMACHINE="TRW RH-32"
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3825 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI() local
3831 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH); in lowerSMUL_LOHI()