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Searched refs:RC1 (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonPatternsV65.td43 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
49 RC1:$Vv),
54 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
60 RC1:$Vv),
65 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
71 RC1:$Vv),
H A DHexagonGenInsert.cpp340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()() local
341 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
343 const BitTracker::BitValue &V1 = RC1[i], &V2 = RC2[i]; in operator ()()
357 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()() local
359 uint16_t W1 = RC1.width(), W2 = RC2.width(); in operator ()()
373 const BitTracker::BitValue &V1 = RC1[Bit1], V2 = RC2[Bit2]; in operator ()()
H A DHexagonBitSimplify.cpp231 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
342 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual() argument
347 if (RC1[B1+i].Type == BitTracker::BitValue::Ref && RC1[B1+i].RefI.Reg == 0) in isEqual()
352 if (RC1[B1+i] != RC2[B2+i]) in isEqual()
/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dnorecurse.ll263 ; IS__TUNIT____-NEXT: [[RC1:%.*]] = call i1 @rec(i1 noundef true)
264 ; IS__TUNIT____-NEXT: br i1 [[RC1]], label [[T:%.*]], label [[F:%.*]]
269 ; IS__TUNIT____-NEXT: ret i1 [[RC1]]
274 ; IS__CGSCC____-NEXT: [[RC1:%.*]] = call noundef i1 @rec(i1 noundef true)
275 ; IS__CGSCC____-NEXT: br i1 [[RC1]], label [[T:%.*]], label [[F:%.*]]
280 ; IS__CGSCC____-NEXT: ret i1 [[RC1]]
H A Dvalue-simplify.ll1429 ; IS__TUNIT_OPM-NEXT: [[RC1:%.*]] = call i1 @ret(i1 noundef [[P]]) #[[ATTR10]]
1430 ; IS__TUNIT_OPM-NEXT: ret i1 [[RC1]]
1441 ; IS__TUNIT_NPM-NEXT: [[RC1:%.*]] = call i1 @ret(i1 noundef [[P]]) #[[ATTR9]]
1442 ; IS__TUNIT_NPM-NEXT: ret i1 [[RC1]]
1453 ; IS__CGSCC_OPM-NEXT: [[RC1:%.*]] = call noundef i1 @ret(i1 noundef [[P]]) #[[ATTR13]]
1454 ; IS__CGSCC_OPM-NEXT: ret i1 [[RC1]]
1465 ; IS__CGSCC_NPM-NEXT: [[RC1:%.*]] = call noundef i1 @ret(i1 noundef [[P]]) #[[ATTR12]]
1466 ; IS__CGSCC_NPM-NEXT: ret i1 [[RC1]]
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DLazyCallGraphTest.cpp2052 LazyCallGraph::RefSCC &RC1 = *I++; in TEST() local
2056 ASSERT_EQ(2, RC1.size()); in TEST()
2057 LazyCallGraph::SCC &C1 = RC1[0]; in TEST()
2058 LazyCallGraph::SCC &C2 = RC1[1]; in TEST()
2088 RC1.replaceNodeFunction(DN, E); in TEST()
2147 LazyCallGraph::RefSCC &RC1 = *I++; in TEST() local
2151 ASSERT_EQ(2, RC1.size()); in TEST()
2152 LazyCallGraph::SCC &C1 = RC1[0]; in TEST()
2153 LazyCallGraph::SCC &C2 = RC1[1]; in TEST()
2171 EXPECT_EQ(&RC1, &*I++); in TEST()
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/
H A Dpro-type-static-cast-downcast.cpp79 auto RC1 = static_cast<const Derived&>(ConstRefToBase); in references() local
H A Dpro-type-cstyle-cast.cpp102 auto RC1 = (const Derived&)ConstRefToBase; in references() local
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp2198 CodeGenRegisterClass *RC1 = RC; in inferCommonSubClass() local
2200 if (RC1 == RC2) in inferCommonSubClass()
2204 const CodeGenRegister::Vec &Memb1 = RC1->getMembers(); in inferCommonSubClass()
2218 if (RC2->RSI.hasStricterSpillThan(RC1->RSI)) in inferCommonSubClass()
2219 std::swap(RC1, RC2); in inferCommonSubClass()
2221 getOrCreateSubClass(RC1, &Intersection, in inferCommonSubClass()
2222 RC1->getName() + "_and_" + RC2->getName()); in inferCommonSubClass()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegAllocFast.cpp1221 const TargetRegisterClass &RC1 = *MRI->getRegClass(Reg1); in allocateInstruction() local
1226 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
1229 bool SmallClass1 = ClassSize1 < RegClassDefCounts[RC1.getID()]; in allocateInstruction()
/llvm-project-15.0.7/llvm/docs/
H A DReleaseProcess.rst42 fixed between RC1 and RC2, but not so much at the end of it.
H A DHowToReleaseLLVM.rst328 #. *Before RC1* Patches should be limited to bug fixes, important optimization
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp865 auto RC1 = MRI.getRegClass(SrcReg1); in PPCEmitCmp() local
886 if (isVSSRCRegClass(RC1)) in PPCEmitCmp()
906 } else if (isVSFRCRegClass(RC1) || (RC2 && isVSFRCRegClass(RC2))) { in PPCEmitCmp()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaOverload.cpp9928 Expr *RC1 = Cand1.Function->getTrailingRequiresClause(); in isBetterOverloadCandidate() local
9930 if (RC1 && RC2) { in isBetterOverloadCandidate()
9932 if (S.IsAtLeastAsConstrained(Cand1.Function, {RC1}, Cand2.Function, {RC2}, in isBetterOverloadCandidate()
9934 S.IsAtLeastAsConstrained(Cand2.Function, {RC2}, Cand1.Function, {RC1}, in isBetterOverloadCandidate()
9939 } else if (RC1 || RC2) { in isBetterOverloadCandidate()
9940 return RC1 != nullptr; in isBetterOverloadCandidate()