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/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A DcapitalizedEndloop.s6 { R0 = mpyi(R0,R0) } : endloop0
7 { R0 = mpyi(R0,R0) } : ENDLOOP0
8 { R0 = mpyi(R0,R0) }:endloop0
10 { R0 = mpyi(R0,R0) } : endloop1
11 { R0 = mpyi(R0,R0) } : ENDLOOP1
12 { R0 = mpyi(R0,R0) }:endloop1
14 { R0 = mpyi(R0,R0) } : endloop01
15 { R0 = mpyi(R0,R0) } : ENDLOOP01
16 { R0 = mpyi(R0,R0) }:endloop01
18 { R0 = mpyi(R0,R0) } : endloop0 : endloop1
[all …]
H A Dv62_all.s5 V0.b=vsplat(R0)
10 V0.h=vsplat(R0)
15 Q0=vsetq2(R0)
85 V0=vand(!Q0,R0)
90 V0|=vand(!Q0,R0)
174 if (!P0) V0=vmem(R0+#04)
184 if (!P0) V0=vmem(R0++M0)
327 if (P0) V0=vmem(R0+#04)
337 if (P0) V0=vmem(R0++M0)
396 V0.ub=vlsr(V0.ub,R0)
[all …]
H A Dv65_all.s11 V0.uw+=vmpye(V0.uh,R0.uh)
21 vscatter(R0,M0,V0.w).w=V0
26 vscatter(R0,M0,V0.h).h=V0
41 vmem(R0+#0):scatter_release
46 vtmp.h=vgather(R0,M0,V0.h).h
51 vscatter(R0,M0,V1:0.w).h=V0
56 vmem(R0++M0):scatter_release
66 V1:0.h=vmpa(V1:0.ub,R0.ub)
76 vscatter(R0,M0,V0.h).h+=V0
116 V0.uw=vmpye(V0.uh,R0.uh)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dbswap.ll13 ; MIPS32: wsbh $[[R0:[0-9]+]]
17 ; MM: wsbh $[[R0:[0-9]+]]
21 ; MIPS64: wsbh $[[R0:[0-9]+]]
44 ; MIPS32: wsbh $[[R0:[0-9]+]]
46 ; MIPS32: wsbh $[[R0:[0-9]+]]
50 ; MM: wsbh $[[R0:[0-9]+]]
52 ; MM: wsbh $[[R0:[0-9]+]]
56 ; MIPS64: dsbh $[[R0:[0-9]+]]
98 ; MM-DAG: wsbh $[[R0:[0-9]+]]
100 ; MM-DAG: wsbh $[[R0:[0-9]+]]
[all …]
H A Dmips64intldst.ll19 ; CHECK-N64: lb ${{[0-9]+}}, 0($[[R0]])
22 ; CHECK-N32: lb ${{[0-9]+}}, 0($[[R0]])
32 ; CHECK-N64: lh ${{[0-9]+}}, 0($[[R0]])
35 ; CHECK-N32: lh ${{[0-9]+}}, 0($[[R0]])
45 ; CHECK-N64: lw ${{[0-9]+}}, 0($[[R0]])
48 ; CHECK-N32: lw ${{[0-9]+}}, 0($[[R0]])
58 ; CHECK-N64: ld ${{[0-9]+}}, 0($[[R0]])
61 ; CHECK-N32: ld ${{[0-9]+}}, 0($[[R0]])
70 ; CHECK-N64: lbu ${{[0-9]+}}, 0($[[R0]])
109 ; CHECK-N64: sb ${{[0-9]+}}, 0($[[R0]])
[all …]
H A Dtls.ll17 ; PIC32-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
18 ; PIC32-DAG: addiu $4, $[[R0]], %tlsgd(t1)
25 ; PIC64-DAG: daddiu $4, $[[R0]], %tlsgd(t1)
31 ; MM-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
32 ; MM-DAG: addiu $4, $[[R0]], %tlsgd(t1)
48 ; PIC32-DAG: addiu $4, $[[R0]], %tlsgd(t2)
63 ; MM-DAG: addiu $4, $[[R0]], %tlsgd(t2)
73 ; PIC32: addu $[[R0:[a-z0-9]+]], $2, $25
74 ; PIC32: addiu $4, $[[R0]], %tlsldm(f3.i)
85 ; PIC64: daddu $[[R0]], $[[R0]], $25
[all …]
H A Dcmov.ll14 ; 32-CMOV-DAG: lw $[[R0:[0-9]+]], %got(i3)
16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
17 ; 32-CMOV-DAG: lw $2, 0($[[R0]])
19 ; 32-CMP-DAG: lw $[[R0:[0-9]+]], %got(i3)
26 ; 64-CMOV-DAG: ldr $[[R0:[0-9]+]]
28 ; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4
57 ; 32-CMOV-DAG: lw $2, 0($[[R0]])
161 ; 32-CMOV-DAG: movz $[[R1]], $6, $[[R0]]
162 ; 32-CMOV-DAG: movz $[[R2]], $7, $[[R0]]
174 ; 64-CMOV: xori $[[R0:[0-9]+]], $4, 234
[all …]
H A Dmno-ldc1-sdc1.ll68 ; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0
73 ; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0
78 ; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0
105 ; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1
110 ; 32R2-BE-PIC-DAG: mthc1 $[[R0]], $f0
115 ; 32R6-BE-PIC-DAG: mthc1 $[[R0]], $f0
240 ; 32R1-DAG: mtc1 $[[R0]], $f0
247 ; 32R2-DAG: mtc1 $[[R0]], $f0
254 ; 32R6-DAG: mtc1 $[[R0]], $f0
290 ; 32R1-DAG: mfc1 $[[R0:[0-9]+]], $f12
[all …]
H A Dtls-static.ll19 ; STATIC32: lui $[[R0:[0-9]+]], %tprel_hi(t1)
20 ; STATIC32: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
26 ; STATIC64: lui $[[R0:[0-9]+]], %tprel_hi(t1)
27 ; STATIC64: daddiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
29 ; STATIC64: daddu $[[R2:[0-9]+]], $3, $[[R0]]
41 ; STATICGP32: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
51 ; STATIC32: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
55 ; STATIC32: addu $[[R1:[0-9]+]], $3, $[[R0]]
63 ; STATIC64: daddu $[[R1:[0-9]+]], $3, $[[R0]]
74 ; MM: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
[all …]
H A Doptimize-fp-math.ll6 ; 32: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
7 ; 32: c.un.s $f[[R0]], $f[[R0]]
9 ; 64: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
10 ; 64: c.un.s $f[[R0]], $f[[R0]]
21 ; 32: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
22 ; 32: c.un.d $f[[R0]], $f[[R0]]
24 ; 64: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
25 ; 64: c.un.d $f[[R0]], $f[[R0]]
H A Dzeroreg.ll19 ; 32R6: seleqz $2, $[[R0]], $4
25 ; 64R6: seleqz $2, $[[R0]], $4
41 ; 32R6: selnez $2, $[[R0]], $4
47 ; 64R6: selnez $2, $[[R0]], $4
61 ; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}})
63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4
69 ; 32R6-DAG: seleqz $2, $[[R0]], $[[CC]]
76 ; 64R6: seleqz $2, $[[R0]], $4
90 ; 32-CMOV-DAG: movz $[[R0]], $zero, $4
96 ; 32R6-DAG: selnez $2, $[[R0]], $[[CC]]
[all …]
H A Dmips64fpldst.ll14 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0)
15 ; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]])
17 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0)
18 ; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]])
26 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0)
27 ; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]])
30 ; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]])
39 ; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]])
42 ; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]])
52 ; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]])
[all …]
H A Dload-store-left-right.ll29 ; MIPS32-EL: lwr $[[R0]], 0($[[R1]])
32 ; MIPS32-EB: lwr $[[R0]], 3($[[R1]])
38 ; MIPS64-EL: lwr $[[R0]], 0($[[R1]])
41 ; MIPS64R2-EL: lwr $[[R0]], 0($[[R1]])
44 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
47 ; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]])
61 ; MIPS32-EL: swr $[[R0]], 0($[[R1]])
64 ; MIPS32-EB: swr $[[R0]], 3($[[R1]])
70 ; MIPS64-EL: swr $[[R0]], 0($[[R1]])
188 ; MIPS64R2-EL-DAG: dext $[[R0]], $[[R0]], 0, 32
[all …]
H A D2009-11-16-CstPoolLoad.ll10 ; PIC-O32: lw $[[R0:[0-9]+]], %got($CPI0_0)
11 ; PIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
12 ; STATIC-O32: lui $[[R0:[0-9]+]], %hi($CPI0_0)
13 ; STATIC-O32: lwc1 $f0, %lo($CPI0_0)($[[R0]])
14 ; PIC-N32: lw $[[R0:[0-9]+]], %got_page(.LCPI0_0)
15 ; PIC-N32: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
16 ; STATIC-N32: lui $[[R0:[0-9]+]], %hi(.LCPI0_0)
17 ; STATIC-N32: lwc1 $f0, %lo(.LCPI0_0)($[[R0]])
18 ; PIC-N64: ld $[[R0:[0-9]+]], %got_page(.LCPI0_0)
19 ; PIC-N64: lwc1 $f0, %got_ofst(.LCPI0_0)($[[R0]])
[all …]
H A Dpr42736.ll8 ; PIC: lui $[[R0:[0-9]+]], 4095
9 ; PIC-NEXT: ori $[[R0]], $[[R0]], 65535
11 ; PIC-NEXT: and $[[R1]], $[[R1]], $[[R0]]
14 ; STATIC: lui $[[R0:[0-9]+]], 4095
15 ; STATIC-NEXT: ori $[[R0]], $[[R0]], 65535
19 ; STATIC-NEXT: and $[[R0]], $[[R1]], $[[R0]]
20 ; STATIC-NEXT: sd $[[R0]]
H A Dint-to-float-conversion.ll9 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
10 ; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
19 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
20 ; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
22 ; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
23 ; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
32 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
33 ; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
42 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
43 ; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
H A Dsint-fp-store_pattern.ll9 ; 32: trunc.w.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
10 ; 32: swc1 $f[[R0]],
20 ; 32: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
21 ; 32: swc1 $f[[R0]],
23 ; 64: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
24 ; 64: swc1 $f[[R0]],
34 ; 64: trunc.l.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
35 ; 64: sdc1 $f[[R0]],
45 ; 64: trunc.l.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
46 ; 64: sdc1 $f[[R0]],
H A Ddext.ll10 ; CHECK: dext $[[R0:[0-9]+]], $[[R0:[0-9]+]], 0, 32
20 ; CHECK: ext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 24
30 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
40 ; CHECK: dextm $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 35
50 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 20
60 ; CHECK: andi $[[R0:[0-9]+]], $[[R1:[0-9]+]], 65535
71 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 20
82 ; CHECK: dextu $[[R0:[0-9]+]], $[[R1:[0-9]+]], 40, 8
92 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
103 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 12
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dintrinsics-overflow.ll13 ; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
18 ; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
22 ; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
37 ; ARM: mov r[[R0]], #1
38 ; ARM: movvc r[[R0]], #0
47 ; THUMBV7: movvc r[[R0]], #0
58 ; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
61 ; ARM: eor r[[R0]], r[[R0]], #1
64 ; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
69 ; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
[all …]
H A Di64_volatile_load_store.ll14 ; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
20 ; CHECK-T2-NEXT: strd [[R0]], [[R1]], [[[ADDR1]]]
25 ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #4]
50 ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #-4]
71 ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #255]
97 ; CHECK-ARMV4T-NEXT: str [[R0]], [[[ADDR1]], #256]
161 ; CHECK-ARMV5TE-NEXT: mov [[R0:r[0-9]+]], #0
168 ; CHECK-T2-NEXT: movs [[R0:r[0-9]+]], #0
170 ; CHECK-T2-NEXT: strd [[R1]], [[R0]], [sp, #8]
175 ; CHECK-ARMV4T-NEXT: mov [[R0:r[0-9]+]], #0
[all …]
H A Dstack_guard_remat.ll9 ;PIC: ldr [[R0:r[0-9]+]], [[LABEL0:LCPI[0-9_]+]]
11 ;PIC: add [[R1:r[0-9]+]], pc, [[R0]]
19 ;NO-PIC: ldr [[R0:r[0-9]+]], [[LABEL0:LCPI[0-9_]+]]
21 ;NO-PIC: ldr {{r[0-9]+}}, [[[R0]]]
32 ;PIC-V7: ldr [[R0]], [pc, [[R0]]]
33 ;PIC-V7: ldr [[R0]], [[[R0]]]
38 ;STATIC-V7: movw [[R0:r[0-9]+]], :lower16:___stack_chk_guard
39 ;STATIC-V7: movt [[R0]], :upper16:___stack_chk_guard
40 ;STATIC-V7: ldr [[R0]], [[[R0]]]
44 ;DYNAMIC-NO-PIC-V7: ldr [[R0]], [[[R0]]]
[all …]
H A Dsubtarget-no-movt.ll17 ; NO-OPTION-COMMON: ldr [[R0:r[0-9]+]], [[L0:.*]]
22 ; USE-MOVT-COMMON: movw [[R0:r[0-9]+]], #52257
23 ; USE-MOVT-COMMON: movt [[R0]], #35037
36 ; NO-OPTION-COMMON: movw [[R0:r[0-9]+]], #52257
37 ; NO-OPTION-COMMON: movt [[R0]], #35037
40 ; USE-MOVT-COMMON: movw [[R0:r[0-9]+]], #52257
41 ; USE-MOVT-COMMON: movt [[R0]], #35037
55 ; NO-OPTION-O0: movw [[R0:r[0-9]+]], #57344
56 ; NO-OPTION-O0: movt [[R0]], #57344
60 ; USE-MOVT-O0: movw [[R0:r[0-9]+]], #57344
[all …]
/llvm-project-15.0.7/llvm/unittests/IR/
H A DMDBuilderTest.cpp47 MDNode *R0 = MDHelper.createRange(A, A); in TEST_F() local
49 EXPECT_EQ(R0, (MDNode *)nullptr); in TEST_F()
63 EXPECT_NE(R0, R1); in TEST_F()
64 EXPECT_GE(R0->getNumOperands(), 1U); in TEST_F()
66 EXPECT_EQ(R0->getOperand(0), R0); in TEST_F()
68 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == nullptr); in TEST_F()
73 MDNode *R0 = MDHelper.createTBAARoot("Root"); in TEST_F() local
75 EXPECT_EQ(R0, R1); in TEST_F()
76 EXPECT_GE(R0->getNumOperands(), 1U); in TEST_F()
77 EXPECT_TRUE(isa<MDString>(R0->getOperand(0))); in TEST_F()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dconvert-int-sm20.ll13 ; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i16_i32_param_{{[0-9]+}}]
14 ; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
21 ; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i16_i64_param_{{[0-9]+}}]
22 ; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
33 ; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i32_i16_param_{{[0-9]+}}]
34 ; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
41 ; CHECK: ld.param.u32 %r[[R0:[0-9]+]], [cvt_i32_i64_param_{{[0-9]+}}]
42 ; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
53 ; CHECK: ld.param.u16 %rd[[R0:[0-9]+]], [cvt_i64_i16_param_{{[0-9]+}}]
54 ; CHECK: st.param.b64 [func_retval{{[0-9]+}}+0], %rd[[R0]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cstmaterialization/
H A Dstack.ll19 ; CHECK-MIPS32: lui $[[R0:[0-9]+]], 16
20 ; CHECK-MIPS32: addiu $[[R0]], $[[R0]], 24
21 ; CHECK-MIPS32: subu $sp, $sp, $[[R0]]
27 ; CHECK-MIPS64: lui $[[R0:[0-9]+]], 1
28 ; CHECK-MIPS64: daddiu $[[R0]], $[[R0]], 32
29 ; CHECK-MIPS64: dsubu $sp, $sp, $[[R0]]
44 ; CHECK-MIPSN32: lui $[[R0:[0-9]+]], 16
45 ; CHECK-MIPSN32: addiu $[[R0]], $[[R0]], 16
46 ; CHECK-MIPSN32: subu $sp, $sp, $[[R0]]

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