Lines Matching refs:R0
28 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
29 ; MIPS32-EL: lwr $[[R0]], 0($[[R1]])
31 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
32 ; MIPS32-EB: lwr $[[R0]], 3($[[R1]])
37 ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
38 ; MIPS64-EL: lwr $[[R0]], 0($[[R1]])
40 ; MIPS64R2-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
41 ; MIPS64R2-EL: lwr $[[R0]], 0($[[R1]])
43 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
44 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
46 ; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
47 ; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]])
60 ; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
61 ; MIPS32-EL: swr $[[R0]], 0($[[R1]])
63 ; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
64 ; MIPS32-EB: swr $[[R0]], 3($[[R1]])
69 ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
70 ; MIPS64-EL: swr $[[R0]], 0($[[R1]])
72 ; MIPS64R2-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
73 ; MIPS64R2-EL: swr $[[R0]], 0($[[R1]])
75 ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
76 ; MIPS64-EB: swr $[[R0]], 3($[[R1]])
78 ; MIPS64R2-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
79 ; MIPS64R2-EB: swr $[[R0]], 3($[[R1]])
106 ; MIPS64-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
107 ; MIPS64-EL: ldr $[[R0]], 0($[[R1]])
109 ; MIPS64R2-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
110 ; MIPS64R2-EL: ldr $[[R0]], 0($[[R1]])
112 ; MIPS64-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
113 ; MIPS64-EB: ldr $[[R0]], 7($[[R1]])
115 ; MIPS64R2-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
116 ; MIPS64R2-EB: ldr $[[R0]], 7($[[R1]])
129 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
130 ; MIPS32-EL: lwr $[[R0]], 0($[[R1]])
132 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
133 ; MIPS32-EB: lwr $[[R0]], 3($[[R1]])
141 ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
142 ; MIPS64-EL: lwr $[[R0]], 0($[[R1]])
144 ; MIPS64R2-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
145 ; MIPS64R2-EL: lwr $[[R0]], 0($[[R1]])
147 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
148 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
150 ; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
151 ; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]])
179 ; MIPS64-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
180 ; MIPS64-EL-DAG: lwr $[[R0]], 0($[[R1]])
184 ; MIPS64-EL-DAG: and ${{[0-9]+}}, $[[R0]], $[[R4]]
186 ; MIPS64R2-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
187 ; MIPS64R2-EL-DAG: lwr $[[R0]], 0($[[R1]])
188 ; MIPS64R2-EL-DAG: dext $[[R0]], $[[R0]], 0, 32
190 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
191 ; MIPS64-EB: lwr $[[R0]], 3($[[R1]])
193 ; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
194 ; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]])
195 ; MIPS64R2-EB: dext $[[R0]], $[[R0]], 0, 32
223 ; MIPS64-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
224 ; MIPS64-EL: sdr $[[R0]], 0($[[R1]])
226 ; MIPS64R2-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]])
227 ; MIPS64R2-EL: sdr $[[R0]], 0($[[R1]])
229 ; MIPS64-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
230 ; MIPS64-EB: sdr $[[R0]], 7($[[R1]])
232 ; MIPS64R2-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
233 ; MIPS64R2-EB: sdr $[[R0]], 7($[[R1]])
246 ; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
247 ; MIPS32-EL: swr $[[R0]], 0($[[R1]])
249 ; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
250 ; MIPS32-EB: swr $[[R0]], 3($[[R1]])
255 ; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
256 ; MIPS64-EL: swr $[[R0]], 0($[[R1]])
258 ; MIPS64R2-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
259 ; MIPS64R2-EL: swr $[[R0]], 0($[[R1]])
261 ; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
262 ; MIPS64-EB: swr $[[R0]], 3($[[R1]])
264 ; MIPS64R2-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
265 ; MIPS64R2-EB: swr $[[R0]], 3($[[R1]])