1; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 \
2; RUN:   | FileCheck %s -check-prefix=MIPS32
3; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
4; RUN:   | FileCheck %s -check-prefix=MM
5; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 \
6; RUN:   | FileCheck %s -check-prefix=MIPS64
7; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 -mattr=+mips16 \
8; RUN:   | FileCheck %s -check-prefix=MIPS16
9
10define i32 @bswap32(i32 signext %x) nounwind readnone {
11entry:
12; MIPS32-LABEL: bswap32:
13; MIPS32: wsbh $[[R0:[0-9]+]]
14; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
15
16; MM-LABEL: bswap32:
17; MM: wsbh $[[R0:[0-9]+]]
18; MM: rotr ${{[0-9]+}}, $[[R0]], 16
19
20; MIPS64-LABEL: bswap32:
21; MIPS64: wsbh $[[R0:[0-9]+]]
22; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
23
24; MIPS16-LABEL: bswap32:
25; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
26; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
27; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8
28; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
29; MIPS16-DAG: li  $[[R4:[0-9]+]], 65280
30; MIPS16-DAG: and $[[R4]], $[[R0]]
31; MIPS16-DAG: or  $[[R1]], $[[R4]]
32; MIPS16-DAG: lw  $[[R7:[0-9]+]], $CPI
33; MIPS16-DAG: and $[[R7]], $[[R2]]
34; MIPS16-DAG: or  $[[R3]], $[[R7]]
35; MIPS16-DAG: or  $[[R3]], $[[R1]]
36
37  %or.3 = call i32 @llvm.bswap.i32(i32 %x)
38  ret i32 %or.3
39}
40
41define i64 @bswap64(i64 signext %x) nounwind readnone {
42entry:
43; MIPS32-LABEL: bswap64:
44; MIPS32: wsbh $[[R0:[0-9]+]]
45; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
46; MIPS32: wsbh $[[R0:[0-9]+]]
47; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
48
49; MM-LABEL: bswap64:
50; MM: wsbh $[[R0:[0-9]+]]
51; MM: rotr ${{[0-9]+}}, $[[R0]], 16
52; MM: wsbh $[[R0:[0-9]+]]
53; MM: rotr ${{[0-9]+}}, $[[R0]], 16
54
55; MIPS64-LABEL: bswap64:
56; MIPS64: dsbh $[[R0:[0-9]+]]
57; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
58
59; MIPS16-LABEL: bswap64:
60; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8
61; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
62; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 8
63; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 24
64; MIPS16-DAG: li  $[[R4:[0-9]+]], 65280
65; MIPS16-DAG: and $[[R0]], $[[R4]]
66; MIPS16-DAG: or  $[[R1]], $[[R0]]
67; MIPS16-DAG: lw  $[[R7:[0-9]+]], 1f
68; MIPS16-DAG: and $[[R2]], $[[R7]]
69; MIPS16-DAG: or  $[[R3]], $[[R2]]
70; MIPS16-DAG: or  $[[R3]], $[[R1]]
71; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
72; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
73; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8
74; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
75; MIPS16-DAG: and $[[R0]], $[[R4]]
76; MIPS16-DAG: or  $[[R1]], $[[R0]]
77; MIPS16-DAG: and $[[R2]], $[[R7]]
78; MIPS16-DAG: or  $[[R3]], $[[R2]]
79; MIPS16-DAG: or  $[[R3]], $[[R1]]
80
81  %or.7 = call i64 @llvm.bswap.i64(i64 %x)
82  ret i64 %or.7
83}
84
85define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone {
86entry:
87; MIPS32-LABEL: bswapv4i32:
88; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
89; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
90; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
91; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
92; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
93; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
94; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
95; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
96
97; MM-LABEL: bswapv4i32:
98; MM-DAG: wsbh $[[R0:[0-9]+]]
99; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
100; MM-DAG: wsbh $[[R0:[0-9]+]]
101; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
102; MM-DAG: wsbh $[[R0:[0-9]+]]
103; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
104; MM-DAG: wsbh $[[R0:[0-9]+]]
105; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
106
107; MIPS64-LABEL: bswapv4i32:
108; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
109; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
110; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
111; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
112; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
113; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
114; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
115; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
116
117; Don't bother with a MIPS16 version. It's just bswap32 repeated four times and
118; would be very long
119
120  %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x)
121  ret <4 x i32> %ret
122}
123
124declare i32 @llvm.bswap.i32(i32) nounwind readnone
125
126declare i64 @llvm.bswap.i64(i64) nounwind readnone
127
128declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
129