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Searched refs:Quad (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/clang/test/CodeGen/
H A D2002-07-14-MiscTests3.c16 struct Quad { struct
24 struct Quad GlobalQuad = { 4, {1, 2}, 0, 3, 156 }; argument
43 static int F0(struct Quad Q, int i) { /* Pass Q by value */ in F0()
44 struct Quad R; in F0()
51 int F1(struct Quad *Q, int i) { /* Pass Q by address */ in F1()
52 struct Quad R; in F1()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA8.td778 // Quad-register FP Unary
797 // Quad-register FP Binary
803 // Quad-register FP VMUL
819 // Quad-register Permute Move
853 // Quad-register Permute
891 // Quad-register Reciprical Step
899 // Quad-register Integer Count
909 // Quad-register Integer Unary
925 // Quad-register Integer Binary
958 // Quad-register Integer Shift
[all …]
H A DARMScheduleA9.td1284 // Quad-register Integer Unary
1320 // Quad-register Integer Binary
1356 // Quad-register Integer Shift
1429 // Quad-register Integer Count
1577 // Quad-register Permute Move
1645 // Quad-register FP Unary
1686 // Quad-register FP Binary
1699 // Quad-register FP VMUL
1757 // Quad-register Reciprical Step
1775 // Quad-register Permute
[all …]
/llvm-project-15.0.7/llvm/unittests/DebugInfo/DWARF/
H A DDWARFDebugLineTest.cpp86 {{0x11223344, LineTable::Quad}}); in setupParser()
723 LT.addExtendedOpcode(9, DW_LNE_set_address, {{Addr2, LineTable::Quad}});
890 {{0x1122334455667788, LineTable::Quad}});
895 {{0x99aabbccddeeff00, LineTable::Quad}});
933 {{0xabcd, LineTable::Quad}});
954 {{SpecialAddr, LineTable::Quad}});
967 {{AdvancePCAddr, LineTable::Quad}});
1377 {{0x1234567890abcdef, LineTable::Quad}});
1470 {{0x123456789abcdef, LineTable::Quad}});
1824 ValueAndLengths{{0x1234567890abcdef, LineTable::Quad}},
[all …]
H A DDwarfGenerator.h174 enum ValueLength { Byte = 1, Half = 2, Long = 4, Quad = 8, ULEB, SLEB }; enumerator
H A DDwarfGenerator.cpp252 case Quad: in writeData()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dpr18663.ll41 %"struct.std::_Vector_base.38.34" = type { %"struct.std::_Vector_base<Quad, std::allocator<Quad> >:…
42 …"struct.std::_Vector_base<Quad, std::allocator<Quad> >::_Vector_impl.33" = type { %class.Quad.32*,…
43 %class.Quad.32 = type { [4 x i32] }
/llvm-project-15.0.7/compiler-rt/
H A DCREDITS.TXT28 D: IEEE Quad-precision functions
/llvm-project-15.0.7/llvm/test/ExecutionEngine/JITLink/X86/
H A DMachO_x86-64_relocations.s142 # Check X86_64_RELOC_SUBTRACTOR Quad/Long in anonymous storage with anonymous
201 # X86_64_RELOC_SUBTRACTOR Quad/Long in named storage with anonymous minuend
219 # Check X86_64_RELOC_SUBTRACTOR Quad/Long in named storage with minuend and subtrahend.
/llvm-project-15.0.7/llvm/test/ExecutionEngine/JITLink/AArch64/
H A DMachO_arm64_relocations.s165 # Check ARM64_RELOC_SUBTRACTOR Quad/Long in anonymous storage with anonymous
218 # ARM64_RELOC_SUBTRACTOR Quad/Long in named storage with anonymous minuend
236 # Check ARM64_RELOC_SUBTRACTOR Quad/Long in named storage with minuend and subtrahend.
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsics.h126 Quad, enumerator
/llvm-project-15.0.7/lld/test/MachO/
H A Dloh-adrp-ldr.s109 ## Quad precision FP read
/llvm-project-15.0.7/clang/utils/TableGen/
H A DNeonEmitter.cpp280 void applyTypespec(bool &Quad);
790 void Type::applyTypespec(bool &Quad) { in applyTypespec() argument
804 Quad = true; in applyTypespec()
807 Quad = true; in applyTypespec()
852 Bitwidth = Quad ? 128 : 64; in applyTypespec()
/llvm-project-15.0.7/llvm/lib/IR/
H A DFunction.cpp1037 OutputTable.push_back(IITDescriptor::get(IITDescriptor::Quad, 0)); in DecodeIITType()
1290 case IITDescriptor::Quad: return Type::getFP128Ty(Context); in DecodeFixedType()
1476 case IITDescriptor::Quad: return !Ty->isFP128Ty(); in matchIntrinsicType()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt365 - Round to Quad-Precision Integer: xsrqpi xsrqpix
372 - Round Quad-Precision to Double-Extended Precision (fp80): xsrqpxp
H A DPPCScheduleP9.td118 // Only one DFU (Decimal Floating Point and Quad Precision) unit.
H A DP9InstrResources.td22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
H A DPPCInstrVSX.td1354 // Quad-Precision Scalar Move Instructions:
1369 // Quad-Precision Scalar Floating-Point Arithmetic Instructions:
1471 // Quad-Precision Floating-Point Conversion Instructions:
1517 // Round to Quad-Precision Integer [with Inexact]
1521 // Round Quad-Precision to Double-Extended Precision (fp80)
/llvm-project-15.0.7/llvm/test/MC/PowerPC/
H A Dvsx.s754 # Round to Quad-Precision Integer [with Inexact]
762 # Round Quad-Precision to Double-Extended Precision
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllc-pipeline.ll109 ; GCN-O0-NEXT: SI Whole Quad Mode
325 ; GCN-O1-NEXT: SI Whole Quad Mode
615 ; GCN-O1-OPTS-NEXT: SI Whole Quad Mode
906 ; GCN-O2-NEXT: SI Whole Quad Mode
1211 ; GCN-O3-NEXT: SI Whole Quad Mode
/llvm-project-15.0.7/mlir/test/Dialect/LLVMIR/
H A Droundtrip.mlir139 // Extended and Quad floating point
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp6561 bool Quad = Type.isQuad(); in EmitCommonNeonBuiltinExpr() local
6609 llvm::Type *VTy = llvm::FixedVectorType::get(Int8Ty, Quad ? 16 : 8); in EmitCommonNeonBuiltinExpr()
6689 Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, Quad), in EmitCommonNeonBuiltinExpr()
6696 Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float16, false, Quad), in EmitCommonNeonBuiltinExpr()
11223 bool Quad = false; in EmitAArch64BuiltinExpr() local
11225 Quad = true; in EmitAArch64BuiltinExpr()
11228 GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float64, false, Quad)); in EmitAArch64BuiltinExpr()