Home
last modified time | relevance | path

Searched refs:PostRASchedulerID (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVTargetMachine.cpp120 disablePass(&PostRASchedulerID); in addPostRegAlloc()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DPasses.h216 extern char &PostRASchedulerID;
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp308 disablePass(&PostRASchedulerID); in addIRPasses()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetMachine.cpp491 disablePass(&PostRASchedulerID); in addPostRegAlloc()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp560 addPass(&PostRASchedulerID); in addPreSched2()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp396 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); in PPCPassConfig()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetPassConfig.cpp292 if (StandardID == &PostRASchedulerID) in overridePass()
1230 addPass(&PostRASchedulerID); in addMachinePasses()
H A DPostRASchedulerList.cpp197 char &llvm::PostRASchedulerID = PostRAScheduler::ID; member in llvm
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetMachine.cpp463 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); in AArch64PassConfig()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.cpp912 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); in GCNPassConfig()