Home
last modified time | relevance | path

Searched refs:PRE_DEC (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp209 } else if (N->getAddressingMode() == ISD::PRE_DEC) { in matchLSNode()
242 if (LSBase->getAddressingMode() == ISD::PRE_DEC || in matchLSNode()
H A DSelectionDAGDumper.cpp506 case ISD::PRE_DEC: return "<pre-dec>"; in getIndexedModeName()
H A DDAGCombiner.cpp16227 if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked, in CombineToPreIndexedLoadStore()
16405 int X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
16406 int Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; in CombineToPreIndexedLoadStore()
24596 : (LSN->getAddressingMode() == ISD::PRE_DEC) in mayAlias()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp129 (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) { in selectIndexedLoad()
135 bool isPre = (AM == ISD::PRE_DEC); in selectIndexedLoad()
H A DAVRISelLowering.cpp120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
121 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
125 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
975 AM = ISD::PRE_DEC; in getPreIndexedAddressParts()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1373 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
H A DBasicTTIImpl.h184 return ISD::PRE_DEC; in getISDIndexedMode()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1590 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1697 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
1761 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1777 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
H A DARMInstrMVE.td7121 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
7205 …turn cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::PRE_INC || AM == ISD::PRE_DEC);
H A DARMISelLowering.cpp19678 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1207 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1218 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1388 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad()
H A DAArch64ISelLowering.cpp19963 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()