| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 129 (AM != ISD::POST_INC && AM != ISD::PRE_DEC)) { in selectIndexedLoad()
172 LD->getAddressingMode() != ISD::POST_INC) in selectIndexedProgMemLoad()
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| H A D | AVRISelLowering.cpp | 118 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
119 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
122 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
123 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
1025 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1373 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
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| H A D | BasicTTIImpl.h | 186 return ISD::POST_INC; in getISDIndexedMode()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelDAGToDAG.cpp | 299 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) in isValidIndexedLoad()
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| H A D | MSP430ISelLowering.cpp | 61 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
62 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
1363 AM = ISD::POST_INC; in getPostIndexedAddressParts()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 827 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
863 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
883 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
962 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1080 if (AM != ISD::POST_INC) in SelectAddrMode6Offset()
1393 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1462 ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm7Offset()
1665 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD || in tryT1IndexedLoad()
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| H A D | ARMISelLowering.cpp | 1117 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
1118 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
19736 AM = ISD::POST_INC; in getPostIndexedAddressParts()
19770 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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| H A D | ARMInstrMVE.td | 7126 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
7220 …return cast<MaskedStoreSDNode>(N)->isTruncatingStore() && (AM == ISD::POST_INC || AM == ISD::POST_…
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 507 case ISD::POST_INC: return "<post-inc>"; in getIndexedModeName()
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| H A D | DAGCombiner.cpp | 16465 if (getCombineLoadStoreParts(Use, ISD::POST_INC, ISD::POST_DEC, IsLoad, in shouldCombineToPostInc()
16491 if (!getCombineLoadStoreParts(N, ISD::POST_INC, ISD::POST_DEC, IsLoad, in getPostIndexedLoadStoreOp()
16593 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB); in SplitIndexingFromLoad()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 651 AM = ISD::POST_INC; in getPostIndexedAddressParts()
1790 setIndexedLoadAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
1791 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
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| H A D | HexagonISelLoweringHVX.cpp | 163 setIndexedLoadAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
164 setIndexedStoreAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 1259 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
1265 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19988 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC; in getPostIndexedAddressParts()
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