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Searched refs:OutVT (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp41 EVT OutVT = N->getValueType(0); in ExpandRes_BITCAST() local
42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
67 TLI.hasBigEndianPartOrdering(OutVT, DL)) in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
94 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
186 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
H A DLegalizeIntegerTypes.cpp381 EVT OutVT = N->getValueType(0); in PromoteIntRes_BITCAST() local
5167 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SPLICE() local
5174 EVT OutVT = N->getValueType(0); in PromoteIntRes_EXTRACT_SUBVECTOR() local
5184 if (OutVT.isScalableVector()) { in PromoteIntRes_EXTRACT_SUBVECTOR()
5228 if (OutVT.isScalableVector()) in PromoteIntRes_EXTRACT_SUBVECTOR()
5257 EVT OutVT = N->getValueType(0); in PromoteIntRes_INSERT_SUBVECTOR() local
5281 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_REVERSE() local
5295 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SHUFFLE() local
5302 EVT OutVT = N->getValueType(0); in PromoteIntRes_BUILD_VECTOR() local
5342 EVT OutVT = N->getValueType(0); in PromoteIntRes_ScalarOp() local
[all …]
H A DLegalizeVectorTypes.cpp2928 Lo = DAG.getNode(N->getOpcode(), dl, { OutVT, MVT::Other }, in SplitVecOp_UnaryOp()
2950 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); in SplitVecOp_UnaryOp()
2951 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi); in SplitVecOp_UnaryOp()
3434 EVT OutVT = N->getValueType(0); in SplitVecOp_TruncateHelper() local
3435 ElementCount NumElements = OutVT.getVectorElementCount(); in SplitVecOp_TruncateHelper()
3436 bool IsFloat = OutVT.isFloatingPoint(); in SplitVecOp_TruncateHelper()
3439 unsigned OutElementSize = OutVT.getScalarSizeInBits(); in SplitVecOp_TruncateHelper()
3443 std::tie(LoOutVT, HiOutVT) = DAG.GetSplitDestVTs(OutVT); in SplitVecOp_TruncateHelper()
3504 ISD::STRICT_FP_ROUND, DL, {OutVT, MVT::Other}, in SplitVecOp_TruncateHelper()
3513 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
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H A DDAGCombiner.cpp22121 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); in combineShuffleToVectorExtend() local
22124 if (TLI.isTypeLegal(OutVT)) in combineShuffleToVectorExtend()
22126 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT)) in combineShuffleToVectorExtend()
22129 SDLoc(SVN), OutVT, N0)); in combineShuffleToVectorExtend()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2675 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2678 OutVT = MVT::i16; in truncateVectorWithNARROW()
2682 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithNARROW()
2692 SDValue Res = DAG.getNode(WebAssemblyISD::NARROW_U, DL, OutVT, Lo, Hi); in truncateVectorWithNARROW()
2715 EVT OutVT = N->getValueType(0); in performTruncateCombine() local
2716 if (!OutVT.isVector()) in performTruncateCombine()
2719 EVT OutSVT = OutVT.getVectorElementType(); in performTruncateCombine()
2723 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector())) in performTruncateCombine()
2728 OutVT.getScalarSizeInBits()); in performTruncateCombine()
2730 return truncateVectorWithNARROW(OutVT, In, DL, DAG); in performTruncateCombine()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp4779 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1); in getPermuteNode()
5157 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(OutBits), in insertUnpackIfPrepared() local
5559 EVT OutVT = Op.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5561 unsigned ToBits = OutVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5565 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits), in lowerSIGN_EXTEND_VECTOR_INREG() local
5578 EVT OutVT = Op.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5581 unsigned OutNumElts = OutVT.getVectorNumElements(); in lowerZERO_EXTEND_VECTOR_INREG()
5597 return DAG.getNode(ISD::BITCAST, DL, OutVT, Shuf); in lowerZERO_EXTEND_VECTOR_INREG()
6764 EVT OutVT = N->getValueType(0); in combineINT_TO_FP() local
6765 Type *OutLLVMTy = OutVT.getTypeForEVT(Ctx); in combineINT_TO_FP()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp21979 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithPACK() local
21983 OutVT = MVT::i16; in truncateVectorWithPACK()
21989 OutVT = EVT::getVectorVT(Ctx, OutVT, 128 / OutVT.getSizeInBits()); in truncateVectorWithPACK()
22002 OutVT = EVT::getVectorVT(Ctx, OutVT, SubSizeInBits / OutVT.getSizeInBits()); in truncateVectorWithPACK()
22023 int Scale = 64 / OutVT.getScalarSizeInBits(); in truncateVectorWithPACK()
50156 EVT OutVT = N->getValueType(0); in combineVectorTruncationWithPACKUS() local
50170 EVT OutVT = N->getValueType(0); in combineVectorTruncationWithPACKSS() local
50172 DAG.getValueType(OutVT)); in combineVectorTruncationWithPACKSS()
50183 EVT OutVT = N->getValueType(0); in combineVectorTruncation() local
50184 if (!OutVT.isVector()) in combineVectorTruncation()
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H A DX86InstrSSE.td3761 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3772 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3781 (OutVT (OpNode (ArgVT RC:$src1),
3786 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
3797 (OutVT (OpNode (ArgVT RC:$src1), RC:$src2)))]>,
3806 (OutVT (OpNode (ArgVT RC:$src1),
H A DX86InstrAVX512.td339 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
344 AVX512_maskable_common<O, F, OutVT, Outs,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16316 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); in getPTest() local
16317 SDValue TVal = DAG.getConstant(1, DL, OutVT); in getPTest()
16318 SDValue FVal = DAG.getConstant(0, DL, OutVT); in getPTest()
16336 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test); in getPTest()
19111 SDValue OutVT = DAG.getValueType(RetVT); in performGatherLoadCombine() local
19113 OutVT = DAG.getValueType(HwRetVt); in performGatherLoadCombine()
19118 Base, Offset, OutVT}; in performGatherLoadCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8506 EVT OutVT = Op.getValueType(); in LowerINT_TO_FP() local
8507 if (OutVT.isVector() && OutVT.isFloatingPoint() && in LowerINT_TO_FP()