| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCTLSDynamicCall.cpp | 89 unsigned Opc1, Opc2; in processBlock() local
94 Opc1 = PPC::ADDItlsgdL; in processBlock()
98 Opc1 = PPC::ADDItlsldL; in processBlock()
102 Opc1 = PPC::ADDItlsgdL32; in processBlock()
106 Opc1 = PPC::ADDItlsldL32; in processBlock()
121 Opc1 = PPC::PADDI8pc; in processBlock()
149 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0); in processBlock()
153 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); in processBlock()
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| H A D | PPCISelDAGToDAG.cpp | 5919 unsigned Opc1, Opc2, Opc3; in Select() local
5923 Opc1 = PPC::VSPLTISB; in Select()
5928 Opc1 = PPC::VSPLTISH; in Select()
5934 Opc1 = PPC::VSPLTISW; in Select()
5948 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
5960 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
5962 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
5974 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
5976 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | GCNCreateVOPD.cpp | 64 unsigned Opc1 = FirstMI->getOpcode(); in doReplace() local
66 int NewOpcode = AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1), in doReplace()
78 switch (Opc1) { in doReplace()
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| H A D | GCNHazardRecognizer.cpp | 2083 unsigned Opc1 = MI1->getOpcode(); in checkMAIHazards90A() local
2086 if (!isDGEMM(Opc) && (!ST.hasGFX940Insts() && isDGEMM(Opc1))) { in checkMAIHazards90A()
2091 (Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_e64 || in checkMAIHazards90A()
2092 Opc1 == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64)) in checkMAIHazards90A()
2098 switch (Opc1) { in checkMAIHazards90A()
2152 switch (Opc1) { in checkMAIHazards90A()
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| H A D | SIInstrInfo.cpp | 88 unsigned Opc1 = N1->getMachineOpcode(); in nodesHaveSameOperandValue() local
91 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
182 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
185 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) in areLoadsFromSameBasePtr()
188 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()
211 Offset1Idx -= get(Opc1).NumDefs; in areLoadsFromSameBasePtr()
217 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()
220 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) in areLoadsFromSameBasePtr()
250 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) { in areLoadsFromSameBasePtr()
259 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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| H A D | Mips16ISelLowering.cpp | 571 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, in emitSelT16() argument
609 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSelT16()
636 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, in emitSeliT16() argument
675 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); in emitSeliT16()
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| /llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | ContainerModeling.cpp | 126 BinaryOperator::Opcode Opc1,
960 BinaryOperator::Opcode Opc1, in invalidateIteratorPositions() argument
964 return compare(State, Pos.getOffset(), Offset1, Opc1) && in invalidateIteratorPositions()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 2091 BinaryOperator::BinaryOps Opc1 = B1->getOpcode(); in foldSelectShuffle() local
2093 if (ConstantsAreOp1 && Opc0 != Opc1) { in foldSelectShuffle()
2097 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl) in foldSelectShuffle()
2105 Opc1 = AltB1.Opcode; in foldSelectShuffle()
2110 if (Opc0 != Opc1 || !C0 || !C1) in foldSelectShuffle()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 7143 unsigned Opc1 = Load1->getMachineOpcode(); in areLoadsFromSameBasePtr() local
7145 switch (Opc1) { in areLoadsFromSameBasePtr()
7344 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear() local
7346 if (Opc1 != Opc2) in shouldScheduleLoadsNear()
7349 switch (Opc1) { in shouldScheduleLoadsNear()
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| H A D | X86ISelLowering.cpp | 26540 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
26574 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
26656 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
26734 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
26747 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
26767 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
26770 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
26789 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
26804 if (IntrData->Opc1 != 0) { in LowerINTRINSIC_WO_CHAIN()
26807 Opc = IntrData->Opc1; in LowerINTRINSIC_WO_CHAIN()
[all …]
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| H A D | X86IntrinsicsInfo.h | 48 uint16_t Opc1; member
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 409 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP() local
414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP()
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 7554 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
7563 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
7581 Value *Opc1 = EmitScalarExpr(E->getArg(1)); in EmitARMBuiltinExpr() local
7583 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm}); in EmitARMBuiltinExpr()
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