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Searched refs:OpNode (Results 1 – 25 of 41) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td202 def : Pat<(OpNode
209 def : Pat<(OpNode
238 def : Pat<(OpNode
245 def : Pat<(OpNode
277 def : Pat<(OpNode
285 def : Pat<(OpNode
468 def : Pat<(OpNode
475 def : Pat<(OpNode
499 def : Pat<(OpNode
506 def : Pat<(OpNode
[all …]
H A DVEInstrInfo.td536 SDPatternOperator OpNode = null_frag,
568 SDPatternOperator OpNode = null_frag,
591 SDPatternOperator OpNode = null_frag,
607 SDPatternOperator OpNode = null_frag,
674 [(set Ty:$sx, (OpNode Ty:$sz))]>;
678 [(set Ty:$sx, (OpNode (Ty mimm:$sz)))]>;
764 [(set Tyo:$sx, (OpNode Tyi:$sy))]>;
1058 [(OpNode Ty:$sx, ADDRrri:$addr)]>;
1062 [(OpNode Ty:$sx, ADDRrii:$addr)]>;
1066 [(OpNode Ty:$sx, ADDRzri:$addr)]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
H A DNVPTXInstrInfo.td181 multiclass I3<string OpcStr, SDNode OpNode> {
242 multiclass F3<string OpcStr, SDNode OpNode> {
442 multiclass F2<string OpcStr, SDNode OpNode> {
582 multiclass ADD_SUB_i1<SDNode OpNode> {
1780 : ISET_FORMAT<OpNode, Mode,
1792 : ISET_FORMAT<OpNode, Mode,
2147 [(OpNode (i32 4))]>;
2150 [(OpNode (i32 5))]>;
2154 [(OpNode (i32 6))]>;
2158 [(OpNode (i32 7))]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td6830 asm, ".8b", OpNode, v8i8>;
8274 (OpNode (v4f16 V64:$Rn),
8301 (OpNode (v2f32 V64:$Rn),
8589 (OpNode (v4i16 V64:$Rn),
8602 (OpNode (v8i16 V128:$Rn),
8615 (OpNode (v2i32 V64:$Rn),
8627 (OpNode (v4i32 V128:$Rn),
8647 (OpNode FPR32Op:$Rn,
8663 (OpNode (v4i16 V64:$Rn),
8676 (OpNode (v8i16 V128:$Rn),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrAVX512.td4176 def : Pat<(_.VT (OpNode _.RC:$src0,
4187 def : Pat<(_.VT (OpNode _.RC:$src0,
6582 (_.VT (OpNode
6591 (_.VT (OpNode
6782 (OpNode _.RC:$src2,
6875 (_.VT (OpNode _.RC:$src2,
7397 (OpNode _.RC:$src2,
9347 (OpNode (_.VT
9920 defm NAME: avx512_trunc<opc, OpcodeStr, InVecNode, OpNode, OpNode,
9944 defm NAME: avx512_trunc<opc, OpcodeStr, InVecNode, OpNode, OpNode,
[all …]
H A DX86InstrFMA.td179 SDPatternOperator OpNode,
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
214 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
244 SDPatternOperator OpNode, RegisterClass RC,
247 x86memop, RC, OpNode, sched>;
249 x86memop, RC, OpNode, sched>;
251 x86memop, RC, OpNode, sched>;
405 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
482 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
509 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
[all …]
H A DX86InstrFPStack.td175 multiclass FPBinary_rr<SDPatternOperator OpNode> {
179 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
181 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
183 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
195 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
197 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
202 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
204 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
352 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
354 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
[all …]
H A DX86InstrXOP.td94 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
106 (vt128 (OpNode (vt128 VR128:$src1),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
140 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
146 (vt128 (OpNode (vt128 VR128:$src1), timm:$src2)))]>,
152 (vt128 (OpNode (vt128 (load addr:$src1)), timm:$src2)))]>,
261 (vt128 (OpNode (vt128 VR128:$src1),
267 def : Pat<(OpNode (load addr:$src2),
282 multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
289 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
[all …]
H A DX86InstrSSE.td30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
216 defm V#NAME : sse12_move_rr<OpNode, vt, OpcodeStr,
228 defm NAME : sse12_move_rr<OpNode, vt, OpcodeStr,
1842 [(set RC:$dst, (OpNode RC:$src1,
2110 (vt (OpNode RC:$src1,
2927 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3576 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3742 (vt128 (OpNode (memop addr:$src1),
7967 (vt128 (OpNode VR128:$src1,
7981 (vt256 (OpNode VR256:$src1,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
328 list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
333 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
339 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
366 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
479 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
507 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
523 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode> :
1440 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
[all …]
H A DMipsInstrFPU.td112 SDPatternOperator OpNode= null_frag> :
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
121 SDPatternOperator OpNode = null_frag> {
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
137 SDPatternOperator OpNode = null_frag> :
146 SDPatternOperator OpNode= null_frag> {
203 SDPatternOperator OpNode = null_frag> :
210 SDPatternOperator OpNode = null_frag> :
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
259 SDPatternOperator OpNode = null_frag> :
[all …]
H A DMipsMSAInstrInfo.td1296 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1307 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1311 class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode,
1314 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1324 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1404 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1463 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1498 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
2311 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2658 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[all …]
H A DMicroMipsInstrFPU.td14 SDPatternOperator OpNode = null_frag> {
15 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
20 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
111 SDPatternOperator OpNode = null_frag> {
112 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
116 def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
H A DMicroMipsDSPInstrInfo.td179 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
185 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
215 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
252 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
325 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
330 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
H A DMipsInstrInfo.td1319 SDPatternOperator OpNode = null_frag>:
1332 SDPatternOperator OpNode = null_frag> :
1386 SDPatternOperator OpNode = null_frag,
1399 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1402 SDPatternOperator OpNode = null_frag,
1414 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1431 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
1438 SDPatternOperator OpNode= null_frag> :
1447 SDPatternOperator OpNode= null_frag> :
1457 SDPatternOperator OpNode= null_frag> :
[all …]
H A DMipsCondMov.td36 SDPatternOperator OpNode = null_frag> :
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 SDPatternOperator OpNode = null_frag> :
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
H A DMips16InstrInfo.td1303 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1304 Mips16Pat<(OpNode CPU16Regs:$r),
1310 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1311 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1324 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1333 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1334 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1341 class LoadM16_pat<PatFrag OpNode, Instruction I, ComplexPattern Addr> :
1342 Mips16Pat<(OpNode Addr:$addr), (I Addr:$addr)>;
1358 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td265 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
413 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
414 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
623 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
694 string OpcStr, PatFrag OpNode>
712 string OpcStr, PatFrag OpNode>
799 [(set R0, (OpNode ADDRri:$addr, R0, GPR:$new))]> {
884 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td287 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
298 multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
479 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
482 [(set (Ty GPR:$Rd), (OpNode ADDRrr:$src))]>,
495 class LoadRI<string OpcString, PatFrag OpNode, ValueType Ty>
498 [(set (Ty GPR:$Rd), (OpNode ADDRri:$src))]>,
597 class StoreRR<string OpcString, PatFrag OpNode, ValueType Ty>
600 [(OpNode (Ty GPR:$Rd), ADDRrr:$dst)]>,
614 class StoreRI<string OpcString, PatFrag OpNode, ValueType Ty>
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2976 (OpNode (TyQ QPR:$src1),
2988 (OpNode (TyQ QPR:$src1),
2997 SDNode OpNode>
3071 (TyQ (OpNode (TyD DPR:$Vn),
3080 (TyQ (OpNode (TyD DPR:$Vn),
3455 SDNode OpNode> {
3710 SDNode OpNode> {
7389 : NEONFPPat<(f32 (OpNode SPR:$a)),
7433 : NEONFPPat<(f32 (OpNode GPR:$a)),
7441 : NEONFPPat<(i32 (OpNode SPR:$a)),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td216 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
230 SDNode OpNode> {
239 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
242 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
251 SDNode OpNode> {
262 SDNode OpNode> {
271 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
274 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
294 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
296 [(OpNode immU6:$a)]>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td132 class PatFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
133 : Pat<(OpNode RegTy:$fj), (Inst $fj)>;
134 class PatFprFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
135 : Pat<(OpNode RegTy:$fj, RegTy:$fk), (Inst $fj, $fk)>;
/llvm-project-15.0.7/polly/lib/Support/
H A DScopHelper.cpp689 auto *OpNode = dyn_cast<MDNode>(X.get()); in findNamedMetadataNode() local
690 if (!OpNode) in findNamedMetadataNode()
693 auto *OpName = dyn_cast<MDString>(OpNode->getOperand(0)); in findNamedMetadataNode()
697 return OpNode; in findNamedMetadataNode()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZk.td136 class PatGprGprByteSelect<SDPatternOperator OpNode, RVInst Inst>
137 : Pat<(OpNode GPR:$rs1, GPR:$rs2, i8:$imm),

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