Lines Matching refs:OpNode
1319 SDPatternOperator OpNode = null_frag>:
1322 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1332 SDPatternOperator OpNode = null_frag> :
1335 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1361 SDPatternOperator OpNode = null_frag,
1365 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1370 SDPatternOperator OpNode = null_frag>:
1373 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
1386 SDPatternOperator OpNode = null_frag,
1390 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
1397 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1399 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1402 SDPatternOperator OpNode = null_frag,
1405 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
1411 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
1414 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1418 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1422 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
1428 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
1431 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
1438 SDPatternOperator OpNode= null_frag> :
1441 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
1447 SDPatternOperator OpNode= null_frag> :
1450 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
1457 SDPatternOperator OpNode= null_frag> :
1459 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
1465 SDPatternOperator OpNode= null_frag> :
1467 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
1691 SDPatternOperator OpNode, InstrItinClass Itin,
1695 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
1704 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
1709 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
1723 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
1725 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;