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/llvm-project-15.0.7/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp30 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr); in getDescriptions()
32 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1); in getDescriptions()
34 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2); in getDescriptions()
36 Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4); in getDescriptions()
45 Descriptions[DW_OP_pick] = Desc(Op::Dwarf2, Op::Size1); in getDescriptions()
80 Descriptions[DW_OP_bregx] = Desc(Op::Dwarf2, Op::SizeLEB, Op::SignedSizeLEB); in getDescriptions()
91 Descriptions[DW_OP_bit_piece] = Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeLEB); in getDescriptions()
93 Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeBlock); in getDescriptions()
96 Desc(Op::Dwarf4, Op::SizeLEB, Op::WasmLocationArg); in getDescriptions()
106 Desc(Op::Dwarf5, Op::SizeLEB, Op::BaseTypeRef); in getDescriptions()
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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPISelLowering.cpp23 VECustomDAG CDAG(DAG, Op); in splitMaskArithmetic()
26 SDValue A = Op->getOperand(0); in splitMaskArithmetic()
27 SDValue B = Op->getOperand(1); in splitMaskArithmetic()
32 unsigned Opc = Op.getOpcode(); in splitMaskArithmetic()
48 VECustomDAG CDAG(DAG, Op); in lowerToVVP()
87 {Op->getOperand(0), Op->getOperand(1), Mask, AVL}); in lowerToVVP()
326 VECustomDAG CDAG(DAG, Op); in legalizeInternalVectorOp()
388 CDAG.getNode(Op.getOpcode(), ResVT, OpVec, Op->getFlags()); in splitVectorOp()
401 return Op; in legalizePackedAVL()
406 return Op; in legalizePackedAVL()
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H A DVECustomDAG.cpp51 switch (Op.getOpcode()) { in isMaskArithmetic()
222 switch (Op->getOpcode()) { in getNodeChain()
225 return Op->getOperand(0); in getNodeChain()
234 switch (Op->getOpcode()) { in getMemoryPtr()
236 return Op->getOperand(1); in getMemoryPtr()
238 return Op->getOperand(2); in getMemoryPtr()
293 switch (Op->getOpcode()) { in getLoadStoreStride()
295 return Op->getOperand(3); in getLoadStoreStride()
297 return Op->getOperand(2); in getLoadStoreStride()
333 switch (Op->getOpcode()) { in getStoredValue()
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H A DVEISelLowering.h135 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
136 SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const;
146 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
147 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
148 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
150 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
151 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
188 SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const;
189 SDValue lowerVVP_LOAD_STORE(SDValue Op, VECustomDAG &) const;
194 SDValue splitVectorOp(SDValue Op, VECustomDAG &CDAG) const;
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/llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/
H A DReduceOperands.cpp28 Op.set(Reduced); in extractOperandsFromModule()
35 static bool isOne(Use &Op) { in isOne() argument
40 static bool isZero(Use &Op) { in isZero() argument
52 Type *Ty = Op->getType(); in shouldReduceOperand()
69 if (!shouldReduceOperand(Op)) in reduceOperandsOneDeltaPass()
72 Type *Ty = Op->getType(); in reduceOperandsOneDeltaPass()
75 return (isOne(Op) || isZero(Op)) ? nullptr : ConstantInt::get(IntTy, 1); in reduceOperandsOneDeltaPass()
82 if (isOne(Op) || isZero(Op) || isZeroOrOneFP(Op)) in reduceOperandsOneDeltaPass()
106 return isZero(Op) ? nullptr : Constant::getNullValue(Op->getType()); in reduceOperandsZeroDeltaPass()
116 Type *Ty = Op->getType(); in reduceOperandsNaNDeltaPass()
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/llvm-project-15.0.7/clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/
H A Dp8-2a.cpp5 template<typename L, typename R> Op(L, R) -> Op<L, R>;
11 template<typename T, typename U, typename V> constexpr Op<Op<T, U>, V> operator< (Op<T, U> a, V b)… in operator <()
12 template<typename T, typename U, typename V> constexpr Op<Op<T, U>, V> operator<= (Op<T, U> a, V b)… in operator <=()
13 template<typename T, typename U, typename V> constexpr Op<Op<T, U>, V> operator> (Op<T, U> a, V b)… in operator >()
14 template<typename T, typename U, typename V> constexpr Op<Op<T, U>, V> operator>= (Op<T, U> a, V b)… in operator >=()
15 template<typename T, typename U, typename V> constexpr Op<Op<T, U>, V> operator<=>(Op<T, U> a, V b)… in operator <=>()
17 template<typename T, typename U, typename V> constexpr Op<T, Op<U, V>> operator< (T a, Op<U, V> b)… in operator <()
18 template<typename T, typename U, typename V> constexpr Op<T, Op<U, V>> operator<= (T a, Op<U, V> b)… in operator <=()
19 template<typename T, typename U, typename V> constexpr Op<T, Op<U, V>> operator> (T a, Op<U, V> b)… in operator >()
20 template<typename T, typename U, typename V> constexpr Op<T, Op<U, V>> operator>= (T a, Op<U, V> b)… in operator >=()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineOperand.h785 return Op; in CreateImm()
791 return Op; in CreateCImm()
797 return Op; in CreateFPImm()
823 return Op;
830 return Op;
835 return Op; in CreateFI()
843 return Op;
851 return Op;
857 return Op;
865 return Op;
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H A DMachineRegisterInfo.h1024 Op = getNextOperandForReg(Op); in advance()
1036 while (Op && ((!ReturnDefs && Op->isDef()) || in advance()
1038 Op = getNextOperandForReg(Op); in advance()
1046 return Op == x.Op;
1064 } while (Op && Op->getParent() == P);
1083 return Op - &Op->getParent()->getOperand(0); in getOperandNo()
1132 Op = getNextOperandForReg(Op); in advance()
1144 while (Op && ((!ReturnDefs && Op->isDef()) || in advance()
1146 Op = getNextOperandForReg(Op); in advance()
1154 return Op == x.Op;
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp407 SDLoc DL(Op); in lowerSELECT()
1174 SDLoc DL(Op); in lowerLOAD()
1416 SDLoc(Op), Op->getValueType(0)); in lowerMSASplatImm()
1886 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1895 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1905 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1955 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1973 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
2271 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
2418 return Op; in lowerEXTRACT_VECTOR_ELT()
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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DMCInstrDescView.cpp152 if (Op.isExplicit() && !Op.isTied()) { in create()
161 if (Op.isExplicit() && Op.isTied()) in create()
173 if (Op.isReg()) { in create()
179 if (Op.isDef() && Op.isImplicit()) in create()
181 if (Op.isUse() && Op.isImplicit()) in create()
202 return Op.isReg() && Op.isExplicit() && Op.isMemory(); in hasMemoryOperands()
260 if (Op.isUse()) in dump()
262 if (Op.isDef()) in dump()
277 if (Op.isTied()) in dump()
317 return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg); in operator ==()
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H A DParallelSnippetGenerator.cpp128 assert(Op.isReg()); in generateSnippetUsingStaticRenaming()
195 for (const auto &Op : Instr.Operands) { in generateCodeTemplates() local
196 if (Op.isReg() && Op.isImplicit() && !Op.isMemory()) { in generateCodeTemplates()
198 if (Op.isUse()) in generateCodeTemplates()
199 ImplicitUses.set(Op.getImplicitReg()); in generateCodeTemplates()
201 assert(Op.isDef() && "Not a use and not a def?"); in generateCodeTemplates()
202 ImplicitDefs.set(Op.getImplicitReg()); in generateCodeTemplates()
211 for (const auto &Op : Instr.Operands) { in generateCodeTemplates() local
212 if (Op.isReg() && Op.isExplicit() && Op.isDef() && !Op.isMemory()) { in generateCodeTemplates()
236 for (const auto &Op : Instr.Operands) { in generateCodeTemplates() local
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H A DSnippetGenerator.cpp60 if (Op.isDef() && Op.isImplicitReg() && in generateConfigurations()
112 if (Op.isMemory()) in computeRegisterInitialValues()
114 if (Op.isImplicitReg()) in computeRegisterInitialValues()
115 return Op.getImplicitReg(); in computeRegisterInitialValues()
116 if (Op.isExplicit() && IT.getValueFor(Op).isReg()) in computeRegisterInitialValues()
122 if (Op.isUse()) { in computeRegisterInitialValues()
132 if (Op.isDef()) { in computeRegisterInitialValues()
194 assert(ROV.Op); in setRegisterOperandValue()
195 if (ROV.Op->isExplicit()) { in setRegisterOperandValue()
203 assert(ROV.Op->isImplicitReg()); in setRegisterOperandValue()
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/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInst.h135 MCOperand Op; in createReg() local
138 return Op; in createReg()
142 MCOperand Op; in createImm() local
145 return Op; in createImm()
149 MCOperand Op; in createSFPImm() local
152 return Op; in createSFPImm()
156 MCOperand Op; in createDFPImm() local
159 return Op; in createDFPImm()
166 return Op; in createExpr()
173 return Op; in createInst()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h171 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
217 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
267 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
302 EVT getOptimalMemOpType(const MemOp &Op,
365 bool isUndef(SDValue Op) const { in isUndef() argument
366 if (Op.isMachineOpcode()) in isUndef()
368 return Op.getOpcode() == ISD::UNDEF; in isUndef()
383 MVT ty(SDValue Op) const { in ty() argument
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h624 EVT getOptimalMemOpType(const MemOp &Op,
627 LLT getOptimalMemOpLLT(const MemOp &Op,
902 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
905 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1000 SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
1001 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1006 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
1019 SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
1048 SDValue LowerFixedLengthVectorMStoreToSVE(SDValue Op,
1055 SDValue LowerFixedLengthConcatVectorsToSVE(SDValue Op,
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/llvm-project-15.0.7/mlir/test/mlir-pdll/Parser/
H A Dstmt.pdll12 let root: Op;
26 erase _: Op;
46 let var: Op;
63 let var: [Op, Op<dialect.op>];
80 let input: Op<dialect.op>;
81 let var: Op = input;
100 erase _: Op;
118 erase _: Op;
136 erase _: Op;
154 erase _: Op;
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H A Dexpr.pdll12 erase _: Op;
65 let tuple = (firstElt = _: Op);
69 erase _: Op;
84 let op: Op<test.all_single>;
121 // CHECK: `-OperationExpr {{.*}} Type<Op>
143 // CHECK: `-OperationExpr {{.*}} Type<Op>
163 // CHECK: `-OperationExpr {{.*}} Type<Op>
176 // CHECK: `-OperationExpr {{.*}} Type<Op>
189 // CHECK: `-OperationExpr {{.*}} Type<Op>
233 erase _: Op;
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/llvm-project-15.0.7/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp56 if (Op.isReg()) { in printOperand()
58 } else if (Op.isImm()) { in printOperand()
62 printExpr(Op.getExpr(), O); in printOperand()
90 if (Op.isImm()) in printImm64Operand()
92 else if (Op.isExpr()) in printImm64Operand()
93 printExpr(Op.getExpr(), O); in printImm64Operand()
95 O << Op; in printImm64Operand()
101 if (Op.isImm()) { in printBrTargetOperand()
102 int16_t Imm = Op.getImm(); in printBrTargetOperand()
104 } else if (Op.isExpr()) { in printBrTargetOperand()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h417 void computeKnownBitsForTargetNode(const SDValue Op,
422 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
634 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
635 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
636 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
643 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
653 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
663 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
666 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
677 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
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/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGExprComplex.cpp594 if (Op.LHS.second && Op.RHS.second) in EmitBinAdd()
597 ResI = Op.LHS.second ? Op.LHS.second : Op.RHS.second; in EmitBinAdd()
601 assert(Op.LHS.second && Op.RHS.second && in EmitBinAdd()
612 if (Op.LHS.second && Op.RHS.second) in EmitBinSub()
615 ResI = Op.LHS.second ? Op.LHS.second in EmitBinSub()
620 assert(Op.LHS.second && Op.RHS.second && in EmitBinSub()
703 if (Op.LHS.second && Op.RHS.second) { in EmitBinMul()
764 assert((Op.LHS.second || Op.RHS.second) && in EmitBinMul()
776 assert(Op.LHS.second && Op.RHS.second && in EmitBinMul()
792 llvm::Value *LHSr = Op.LHS.first, *LHSi = Op.LHS.second; in EmitBinDiv()
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.td125 def OpMemberDecorateString: Op<5633, (outs),
141 def OpEntryPoint: Op<15, (outs),
234 def OpConstantSampler: Op<45, (outs ID:$res),
269 def OpPtrAccessChain: Op<67, (outs ID:$res),
288 def OpFunction: Op<54, (outs ID:$func),
331 def OpImageFetch: Op<95, (outs ID:$res),
334 def OpImageGather: Op<96, (outs ID:$res),
337 def OpImageDrefGather: Op<97, (outs ID:$res),
341 def OpImageRead: Op<98, (outs ID:$res),
499 def OpBitFieldInsert: Op<201, (outs ID:$res),
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/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h168 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
178 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
179 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
180 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
200 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp312 const auto &Op = N->getOperand(i); in run() local
314 EVT OpVT = Op.getValueType(); in run()
521 SDValue Op = OrigOp; in AnalyzeNewNode() local
530 NewOps.push_back(Op); in AnalyzeNewNode()
531 } else if (Op != OrigOp) { in AnalyzeNewNode()
534 NewOps.push_back(Op); in AnalyzeNewNode()
719 Result->setFlags(Op->getFlags()); in SetPromotedInteger()
721 DAG.transferDbgValues(Op, Result); in SetPromotedInteger()
896 SDLoc dl(Op); in CreateStackStoreLoad()
1025 SDLoc dl(Op); in SplitInteger()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600InstPrinter.cpp97 assert(Op.isImm() || Op.isExpr()); in printLiteral()
98 if (Op.isImm()) { in printLiteral()
99 int64_t Imm = Op.getImm(); in printLiteral()
102 if (Op.isExpr()) { in printLiteral()
144 if (Op.isReg()) { in printOperand()
145 switch (Op.getReg()) { in printOperand()
154 } else if (Op.isImm()) { in printOperand()
155 O << Op.getImm(); in printOperand()
156 } else if (Op.isDFPImm()) { in printOperand()
163 } else if (Op.isExpr()) { in printOperand()
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h117 shouldSimplifyDemandedVectorElts(SDValue Op,
124 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
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