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Searched refs:OffsetIsScalable (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dcluster_stores.ll14 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
15 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
16 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
17 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
18 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
19 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
150 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
151 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
152 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
153 ; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp152 bool OffsetIsScalable; in runOnMachineFunction() local
153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in runOnMachineFunction()
H A DAArch64InstrInfo.h143 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
152 int64_t &Offset, bool &OffsetIsScalable,
H A DAArch64InstrInfo.cpp2546 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, in getMemOperandsWithOffsetWidth() argument
2552 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth()
2564 bool OffsetIsScalable; in getAddrModeFromMemoryOp() local
2565 if (!getMemOperandWithOffset(MemI, Base, Offset, OffsetIsScalable, TRI)) in getAddrModeFromMemoryOp()
2580 bool &OffsetIsScalable, unsigned &Width, in getMemOperandWithOffsetWidth() argument
2618 OffsetIsScalable = Scale.isScalable(); in getMemOperandWithOffsetWidth()
7195 bool OffsetIsScalable; in getOutliningCandidateInfo() local
7199 if (!getMemOperandWithOffset(MI, Base, Offset, OffsetIsScalable, &TRI) || in getOutliningCandidateInfo()
7204 if (OffsetIsScalable) in getOutliningCandidateInfo()
7671 bool OffsetIsScalable; in fixupPostOutline() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h73 bool &OffsetIsScalable, unsigned &Width,
H A DLanaiInstrInfo.cpp796 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, in getMemOperandsWithOffsetWidth() argument
811 OffsetIsScalable = false; in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp1072 bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const { in getMemOperandWithOffset() argument
1075 if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable, in getMemOperandWithOffset()
1180 bool OffsetIsScalable; in describeLoadedValue() local
1224 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, in describeLoadedValue()
1229 if (OffsetIsScalable) in describeLoadedValue()
H A DMachineSink.cpp1018 bool OffsetIsScalable; in SinkingPreventsImplicitNullCheck() local
1019 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in SinkingPreventsImplicitNullCheck()
H A DModuloSchedule.cpp897 bool OffsetIsScalable; in computeDelta() local
898 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
902 if (OffsetIsScalable) in computeDelta()
H A DMachinePipeliner.cpp2123 bool OffsetIsScalable; in computeDelta() local
2124 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) in computeDelta()
2128 if (OffsetIsScalable) in computeDelta()
H A DMachineScheduler.cpp1690 bool OffsetIsScalable; in collectMemOpRecords() local
1693 OffsetIsScalable, Width, TRI)) { in collectMemOpRecords()
1697 << Offset << ", OffsetIsScalable: " << OffsetIsScalable in collectMemOpRecords()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1338 bool &OffsetIsScalable,
1350 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, in getMemOperandsWithOffsetWidth() argument
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h210 bool &OffsetIsScalable, unsigned &Width,
H A DHexagonInstrInfo.cpp3035 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, in getMemOperandsWithOffsetWidth() argument
3037 OffsetIsScalable = false; in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrInfo.h344 bool &OffsetIsScalable, unsigned &Width,
H A DX86InstrInfo.cpp3795 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, in getMemOperandsWithOffsetWidth() argument
3827 OffsetIsScalable = false; in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h642 bool &OffsetIsScalable, unsigned &Width,
H A DPPCInstrInfo.cpp2766 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, in getMemOperandsWithOffsetWidth() argument
2769 OffsetIsScalable = false; in getMemOperandsWithOffsetWidth()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp1920 bool OffsetIsScalable; in schedule() local
1922 OffsetIsScalable, TRI)) in schedule()
H A DSIInstrInfo.h198 bool &OffsetIsScalable, unsigned &Width,
H A DSIInstrInfo.cpp299 int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, in getMemOperandsWithOffsetWidth() argument
305 OffsetIsScalable = false; in getMemOperandsWithOffsetWidth()