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Searched refs:NumVecs (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2107 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2145 if (NumVecs == 1) in SelectVLD()
2148 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
2224 if (NumVecs == 1) { in SelectVLD()
2249 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2423 if (NumVecs != 3) { in SelectVLDSTLane()
2457 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2483 if (NumVecs == 2) { in SelectVLDSTLane()
2950 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2963 if (NumVecs != 3) { in SelectVLDDup()
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H A DARMISelLowering.cpp15603 NumVecs = 1; in TryCombineBaseUpdate()
15607 NumVecs = 2; in TryCombineBaseUpdate()
15611 NumVecs = 3; in TryCombineBaseUpdate()
15615 NumVecs = 4; in TryCombineBaseUpdate()
15619 NumVecs = 2; in TryCombineBaseUpdate()
15624 NumVecs = 3; in TryCombineBaseUpdate()
15629 NumVecs = 4; in TryCombineBaseUpdate()
15634 NumVecs = 2; in TryCombineBaseUpdate()
16186 NumVecs = 2; in CombineVLDDUP()
16189 NumVecs = 3; in CombineVLDDUP()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1495 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1499 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1527 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1531 if (NumVecs == 1) in SelectPostLoad()
1534 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1590 for (unsigned i = 0; i < NumVecs; ++i) in SelectPredicatedLoad()
1595 unsigned ChainIdx = NumVecs; in SelectPredicatedLoad()
1746 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1753 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1791 if (NumVecs == 1) { in SelectPostLoadLane()
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H A DAArch64ISelLowering.cpp12361 template <unsigned NumVecs>
12371 for (unsigned I = 0; I < NumVecs; ++I) in setInfoSVEStN()
17827 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
17832 NumVecs = 2; break; in performNEONPostLDSTCombine()
17834 NumVecs = 3; break; in performNEONPostLDSTCombine()
17836 NumVecs = 4; break; in performNEONPostLDSTCombine()
17838 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
17840 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
17844 NumVecs = 2; break; in performNEONPostLDSTCombine()
17846 NumVecs = 3; break; in performNEONPostLDSTCombine()
[all …]
H A DAArch64TargetTransformInfo.cpp2829 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
2833 for (unsigned N = 0; N < NumVecs; N++) { in getShuffleCost()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DVectorUtils.cpp916 unsigned NumVecs) { in createInterleaveMask() argument
919 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
991 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
992 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
998 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
1000 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
1007 if (NumVecs % 2 != 0) in concatenateVectors()
1008 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
1011 NumVecs = ResList.size(); in concatenateVectors()
1012 } while (NumVecs > 1); in concatenateVectors()
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DVectorUtils.h523 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp187 bool selectVectorLoadIntrinsic(unsigned Opc, unsigned NumVecs,
5567 unsigned NumVecs, in selectVectorLoadIntrinsic() argument
5571 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadIntrinsic()
5584 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in selectVectorLoadIntrinsic()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp10493 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10496 NumVecs = 4; in LowerINTRINSIC_WO_CHAIN()
10500 for (int VecNo = 0; VecNo < NumVecs; VecNo++) { in LowerINTRINSIC_WO_CHAIN()
10503 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
10914 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
10915 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorLoad()
10959 unsigned NumVecs = 2; in LowerVectorStore() local
10962 NumVecs = 4; in LowerVectorStore()
10964 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorStore()
10965 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp16158 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
16161 NumVecs = 4; in EmitPPCBuiltinExpr()
16170 for (unsigned i=0; i<NumVecs; i++) { in EmitPPCBuiltinExpr()