316   void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
323   void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
325   void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
327   void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
328   void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
329   void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
349   void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
350   void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
351   void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
352   void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
353   void SelectPredicatedStore(SDNode *N, unsigned NumVecs, unsigned Scale,
1360 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,  in SelectTable()  argument
1370                                N->op_begin() + Vec0Off + NumVecs);  in SelectTable()
1377   Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));  in SelectTable()
1482 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,  in SelectLoad()  argument
1495   for (unsigned i = 0; i < NumVecs; ++i)  in SelectLoad()
1499   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));  in SelectLoad()
1511 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,  in SelectPostLoad()  argument
1527   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));  in SelectPostLoad()
1531   if (NumVecs == 1)  in SelectPostLoad()
1534     for (unsigned i = 0; i < NumVecs; ++i)  in SelectPostLoad()
1539   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));  in SelectPostLoad()
1567 void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs,  in SelectPredicatedLoad()  argument
1590   for (unsigned i = 0; i < NumVecs; ++i)  in SelectPredicatedLoad()
1595   unsigned ChainIdx = NumVecs;  in SelectPredicatedLoad()
1600 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,  in SelectStore()  argument
1607   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectStore()
1610   SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};  in SelectStore()
1620 void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,  in SelectPredicatedStore()  argument
1626   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectPredicatedStore()
1633       N, Opc_rr, Opc_ri, N->getOperand(NumVecs + 3),  in SelectPredicatedStore()
1636   SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate  in SelectPredicatedStore()
1662 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,  in SelectPostStore()  argument
1671   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostStore()
1675                    N->getOperand(NumVecs + 1), // base register  in SelectPostStore()
1676                    N->getOperand(NumVecs + 2), // Incremental  in SelectPostStore()
1718 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,  in SelectLoadLane()  argument
1725   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectLoadLane()
1736       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();  in SelectLoadLane()
1739                    N->getOperand(NumVecs + 3), N->getOperand(0)};  in SelectLoadLane()
1746   for (unsigned i = 0; i < NumVecs; ++i) {  in SelectLoadLane()
1753   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));  in SelectLoadLane()
1757 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,  in SelectPostLoadLane()  argument
1764   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostLoadLane()
1776       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();  in SelectPostLoadLane()
1781                    N->getOperand(NumVecs + 2),                  // Base register  in SelectPostLoadLane()
1782                    N->getOperand(NumVecs + 3),                  // Incremental  in SelectPostLoadLane()
1787   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));  in SelectPostLoadLane()
1791   if (NumVecs == 1) {  in SelectPostLoadLane()
1798     for (unsigned i = 0; i < NumVecs; ++i) {  in SelectPostLoadLane()
1808   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));  in SelectPostLoadLane()
1812 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,  in SelectStoreLane()  argument
1819   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectStoreLane()
1828       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();  in SelectStoreLane()
1831                    N->getOperand(NumVecs + 3), N->getOperand(0)};  in SelectStoreLane()
1841 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,  in SelectPostStoreLane()  argument
1848   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostStoreLane()
1860       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();  in SelectPostStoreLane()
1863                    N->getOperand(NumVecs + 2), // Base Register  in SelectPostStoreLane()
1864                    N->getOperand(NumVecs + 3), // Incremental  in SelectPostStoreLane()