213   void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
221   void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
229                        unsigned NumVecs, const uint16_t *DOpcodes,
286   void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
307                     unsigned NumVecs, const uint16_t *DOpcodes,
345   SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1932                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1933   unsigned NumRegs = NumVecs;  in GetVLDSTAlign()
1934   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
2097 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {  in isPerfectIncrement()  argument
2099   return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;  in isPerfectIncrement()
2102 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVLD()  argument
2107   assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");  in SelectVLD()
2120   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
2145   if (NumVecs == 1)  in SelectVLD()
2148     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLD()
2165   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
2172       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVLD()
2224   if (NumVecs == 1) {  in SelectVLD()
2235   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLD()
2238   ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));  in SelectVLD()
2240     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));  in SelectVLD()
2244 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVST()  argument
2249   assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");  in SelectVST()
2265   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
2299   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
2301     if (NumVecs == 1) {  in SelectVST()
2307       if (NumVecs == 2)  in SelectVST()
2313         SDValue V3 = (NumVecs == 3)  in SelectVST()
2331       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVST()
2364   SDValue V3 = (NumVecs == 3)  in SelectVST()
2399                                       unsigned NumVecs,  in SelectVLDSTLane()  argument
2403   assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");  in SelectVLDSTLane()
2418     cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();  in SelectVLDSTLane()
2423   if (NumVecs != 3) {  in SelectVLDSTLane()
2425     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDSTLane()
2457     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDSTLane()
2476         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDSTLane()
2483   if (NumVecs == 2) {  in SelectVLDSTLane()
2490     SDValue V3 = (NumVecs == 3)  in SelectVLDSTLane()
2519   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLDSTLane()
2522   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));  in SelectVLDSTLane()
2524     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));  in SelectVLDSTLane()
2782 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,  in SelectMVE_VLD()  argument
2803   EVT DataTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs * 2);  in SelectMVE_VLD()
2811   for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) {  in SelectMVE_VLD()
2824       CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);  in SelectMVE_VLD()
2828   for (i = 0; i < NumVecs; i++)  in SelectMVE_VLD()
2945                                    bool isUpdating, unsigned NumVecs,  in SelectVLDDup()  argument
2950   assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");  in SelectVLDDup()
2963   if (NumVecs != 3) {  in SelectVLDDup()
2965     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDDup()
2997   unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDDup()
3015                  : (NumVecs == 1) ? QOpcodes0[OpcodeIndex]  in SelectVLDDup()
3020         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDDup()
3030   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
3032   } else if (NumVecs == 2) {  in SelectVLDDup()
3058   if (NumVecs == 1) {  in SelectVLDDup()
3064     for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {  in SelectVLDDup()
3069   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));  in SelectVLDDup()
3071     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));  in SelectVLDDup()