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Searched refs:MERGE_VALUES (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h236 MERGE_VALUES, enumerator
/llvm-project-15.0.7/llvm/utils/
H A Dupdate_mir_test_checks.py270 MERGE_VALUES='MV',
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp284 case ISD::MERGE_VALUES: in LegalizeOp()
712 case ISD::MERGE_VALUES: in Expand()
H A DSelectionDAGDumper.cpp174 case ISD::MERGE_VALUES: return "merge_values"; in getOperationName()
H A DSelectionDAGBuilder.cpp901 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); in getCopyFromRegs()
3063 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, in visitLandingPad()
3392 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitSelect()
3801 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInsertValue()
3836 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitExtractValue()
4167 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, in visitLoad()
9120 if (Val.getOpcode() == ISD::MERGE_VALUES) { in visitInlineAsm()
9136 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInlineAsm()
10015 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, in LowerCallTo()
11325 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitFreeze()
H A DInstrEmitter.cpp1163 case ISD::MERGE_VALUES: in EmitSpecialNode()
H A DLegalizeFloatTypes.cpp65 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
1207 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandFloatResult()
H A DSelectionDAG.cpp2943 case ISD::MERGE_VALUES: in computeKnownBits()
3956 case ISD::MERGE_VALUES: in ComputeNumSignBits()
5173 case ISD::MERGE_VALUES: in getNode()
7596 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops); in getMergeValues()
9087 return getNode(ISD::MERGE_VALUES, DL, VTList, {N1, ZeroOverFlow}, Flags); in getNode()
H A DScheduleDAGRRList.cpp706 case ISD::MERGE_VALUES: in EmitNode()
H A DLegalizeVectorTypes.cpp53 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
948 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in SplitVectorResult()
3654 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; in WidenVectorResult()
H A DLegalizeDAG.cpp1078 case ISD::MERGE_VALUES: in LegalizeOp()
2844 case ISD::MERGE_VALUES: in ExpandNode()
H A DLegalizeIntegerTypes.cpp58 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
2398 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandIntegerResult()
H A DTargetLowering.cpp9402 assert(Ret.getOpcode() == ISD::MERGE_VALUES && in expandMULO()
H A DDAGCombiner.cpp1674 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); in visit()
13515 if (Elt.getOpcode() != ISD::MERGE_VALUES) in getBuildPairElt()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1837 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
1838 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2519 assert(S->getOpcode() == ISD::MERGE_VALUES); in LowerHvxOperationWrapper()
2564 assert(Load->getOpcode() == ISD::MERGE_VALUES); in ReplaceHvxNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3990 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4056 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerADDSUBCARRY()
4470 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), in lowerINTRINSIC_WO_CHAIN()
6681 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), in combineFP_ROUND()
6747 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op0), in combineFP_EXTEND()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp737 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
H A DSIISelLowering.cpp5029 if (Res.getOpcode() == ISD::MERGE_VALUES) { in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DREADME.txt1372 it into a MERGE_VALUES with the first definition being an implicit_def. The
H A DX86ISelLowering.cpp27856 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
27877 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
27913 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
27954 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
27967 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC, in LowerINTRINSIC_W_CHAIN()
28094 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), in LowerINTRINSIC_W_CHAIN()
31192 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), in LowerCMP_SWAP()
31700 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), in lowerAtomicArith()
31707 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), in lowerAtomicArith()
31715 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), in lowerAtomicArith()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1418 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC); in LowerXALUO()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4958 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerSignedALUO()
5019 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerUnsignedALUO()
9766 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Carry); in LowerADDSUBCARRY()
9840 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, in LowerFSINCOS()
20446 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values); in LowerDivRem()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp10786 return DAG.getNode(ISD::MERGE_VALUES, dl, {MVT::i128, MVT::Other}, in LowerATOMIC_LOAD_STORE()
14614 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3624 return DAG.getNode(ISD::MERGE_VALUES, DL, VTs, Sum, OutFlag); in lowerADDSUBCARRY()
3650 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerXALUO()