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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h48 MCInst::const_iterator BundleEnd;
50 MCInst::const_iterator DuplexEnd;
57 MCInst const &operator*() const;
94 iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
108 MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
110 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
114 MCInst deriveSubInst(MCInst const &Inst);
117 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
217 MCInst const &instruction(MCInst const &MCB, size_t Index);
241 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h73 void printCPol(const MCInst *MI, unsigned OpNo,
91 void printLWE(const MCInst *MI, unsigned OpNo,
93 void printD16(const MCInst *MI, unsigned OpNo,
97 void printExpVM(const MCInst *MI, unsigned OpNo,
99 void printFORMAT(const MCInst *MI, unsigned OpNo,
101 void printSymbolicFormat(const MCInst *MI,
141 void printFI(const MCInst *MI, unsigned OpNo,
154 void printOpSel(const MCInst *MI, unsigned OpNo,
158 void printNegLo(const MCInst *MI, unsigned OpNo,
160 void printNegHi(const MCInst *MI, unsigned OpNo,
[all …]
H A DR600InstPrinter.h22 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
28 void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
30 void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
31 void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
32 void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
33 void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O);
36 void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printRel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h34 void printInstruction(const MCInst *MI, uint64_t Address,
55 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
57 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
99 void printMemBOption(const MCInst *MI, unsigned OpNum,
123 void printThumbSRImm(const MCInst *MI, unsigned OpNum,
169 void printCPSIMod(const MCInst *MI, unsigned OpNum,
171 void printCPSIFlag(const MCInst *MI, unsigned OpNum,
214 void printPCLabel(const MCInst *MI, unsigned OpNum,
223 void printFBits16(const MCInst *MI, unsigned OpNum,
225 void printFBits32(const MCInst *MI, unsigned OpNum,
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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dinstalias-imm-expanding.s11 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADD
14 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} ADD_MM
19 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADD
23 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} ADD_MM
26 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADDi
31 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADDi
37 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADD
44 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADD
50 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADD
57 # MIPS-NEXT: # <MCInst #{{[0-9]+}} ADD
[all …]
H A Dmicromips-eva.s13 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} PREFE_MM
15 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CACHEE_MM
17 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LLE_MM
19 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SCE_MM
21 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWRE_MM
23 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWLE_MM
25 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWRE_MM
29 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHuE_M
31 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LBE_MM
35 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LHE_MM
[all …]
H A Dmicromips-loadstore-instructions.s27 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWXS_MM
29 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
31 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
33 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
35 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
37 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
39 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWM32_MM
65 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SWP_MM
67 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} LWP_MM
124 # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} SWP_MM
[all …]
H A Dmicromips-fpu-instructions.s29 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CEIL_W_S_MM
31 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} CEIL_W_MM
37 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} FLOOR_W_MM
41 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} ROUND_W_MM
47 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} TRUNC_W_MM
65 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MFC1_MM
67 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MTC1_MM
81 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVT_S_MM
85 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVF_S_MM
97 # CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_F_S_MM
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/MIPS/
H A DEmulateInstructionMIPS.h20 class MCInst; variable
105 bool Emulate_LUI(llvm::MCInst &insn);
107 bool Emulate_SW(llvm::MCInst &insn);
109 bool Emulate_LW(llvm::MCInst &insn);
145 bool Emulate_BAL(llvm::MCInst &insn);
149 bool Emulate_BC(llvm::MCInst &insn);
151 bool Emulate_J(llvm::MCInst &insn);
153 bool Emulate_JAL(llvm::MCInst &insn);
159 bool Emulate_JIC(llvm::MCInst &insn);
161 bool Emulate_JR(llvm::MCInst &insn);
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVInstPrinter.h21 void recordOpExtInstImport(const MCInst *MI);
26 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
28 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
33 void printOpDecorate(const MCInst *MI, raw_ostream &O);
34 void printOpExtInst(const MCInst *MI, raw_ostream &O);
38 void printOpConstantVarOps(const MCInst *MI, unsigned StartIndex,
41 void printExtInst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
51 void printDim(const MCInst *MI, unsigned OpNo, raw_ostream &O);
53 void printSamplerAddressingMode(const MCInst *MI, unsigned OpNo,
59 void printImageChannelDataType(const MCInst *MI, unsigned OpNo,
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h74 void printVRegOperand(const MCInst *MI, unsigned OpNo,
78 void printAddSubImm(const MCInst *MI, unsigned OpNum,
81 void printLogicalImm(const MCInst *MI, unsigned OpNum,
83 void printShifter(const MCInst *MI, unsigned OpNum,
95 void printMemExtend(const MCInst *MI, unsigned OpNum, in printMemExtend()
102 void printCondCode(const MCInst *MI, unsigned OpNum,
125 void printAMNoIndex(const MCInst *MI, unsigned OpNum,
129 void printImmScale(const MCInst *MI, unsigned OpNum,
136 void printPSBHintOp(const MCInst *MI, unsigned OpNum,
207 void printSVERegOp(const MCInst *MI, unsigned OpNum,
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/llvm-project-15.0.7/lldb/source/Plugins/Instruction/MIPS64/
H A DEmulateInstructionMIPS64.h23 class MCInst; variable
94 bool Emulate_LUI(llvm::MCInst &insn);
96 bool Emulate_SD(llvm::MCInst &insn);
98 bool Emulate_LD(llvm::MCInst &insn);
120 bool Emulate_BAL(llvm::MCInst &insn);
124 bool Emulate_BC(llvm::MCInst &insn);
126 bool Emulate_J(llvm::MCInst &insn);
128 bool Emulate_JAL(llvm::MCInst &insn);
134 bool Emulate_JIC(llvm::MCInst &insn);
136 bool Emulate_JR(llvm::MCInst &insn);
[all …]
/llvm-project-15.0.7/bolt/include/bolt/Core/
H A DMCPlusBuilder.h99 MCInst *getAnnotationInst(const MCInst &Inst) const { in getAnnotationInst()
107 MCInst *AnnotationInst = const_cast<MCInst *>(LastOp.getInst()); in getAnnotationInst()
164 void setTailCall(MCInst &Inst);
175 virtual MCInst &Deref() = 0;
185 virtual MCInst &Deref() override { return const_cast<MCInst &>(*Itr); } in Deref()
342 bool equals(const MCInst &A, const MCInst &B, CompFuncTy Comp) const;
882 virtual MCInst::iterator getMemOperandDisp(MCInst &Inst) const { in getMemOperandDisp()
1100 bool clearOffset(MCInst &Inst);
1335 MCInst *&CondBranch, MCInst *&UncondBranch) const { in analyzeBranch()
1922 const MCInst &CallInst, in indirectCallPromotion()
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/llvm-project-15.0.7/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kInstPrinter.h34 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
38 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
44 void printOperand(const MCInst *MI, unsigned opNum, raw_ostream &O);
47 void printMoveMask(const MCInst *MI, unsigned opNum, raw_ostream &O);
50 void printDisp(const MCInst *MI, unsigned opNum, raw_ostream &O);
51 void printARIMem(const MCInst *MI, unsigned opNum, raw_ostream &O);
54 void printARIDMem(const MCInst *MI, unsigned opNum, raw_ostream &O);
55 void printARIIMem(const MCInst *MI, unsigned opNum, raw_ostream &O);
56 void printAbsMem(const MCInst *MI, unsigned opNum, raw_ostream &O);
57 void printPCDMem(const MCInst *MI, uint64_t Address, unsigned opNum,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h24 class MCInst; variable
50 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
56 uint64_t getBinaryCodeForInstr(const MCInst &MI,
63 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
76 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
80 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
84 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
184 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
189 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
243 unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo,
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.h40 void printInstruction(const MCInst *MI, uint64_t Address,
44 bool printAliasInstr(const MCInst *MI, uint64_t Address,
55 void printATBitsAsHint(const MCInst *MI, unsigned OpNo,
58 void printU1ImmOperand(const MCInst *MI, unsigned OpNo,
60 void printU2ImmOperand(const MCInst *MI, unsigned OpNo,
62 void printU3ImmOperand(const MCInst *MI, unsigned OpNo,
64 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
66 void printS5ImmOperand(const MCInst *MI, unsigned OpNo,
68 void printU5ImmOperand(const MCInst *MI, unsigned OpNo,
98 void printMemRegImm(const MCInst *MI, unsigned OpNo,
[all …]
H A DPPCMCCodeEmitter.h38 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
41 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
50 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
53 uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo,
63 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
66 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
90 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
111 uint64_t getBinaryCodeForInstr(const MCInst &MI,
115 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
120 unsigned getInstSizeInBytes(const MCInst &MI) const;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.h27 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
46 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
47 void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
48 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
51 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printbytemem()
54 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printwordmem()
57 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printdwordmem()
76 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printSrcIdx8()
[all …]
H A DX86IntelInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
46 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
48 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
49 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O);
52 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printbytemem()
56 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printwordmem()
60 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printdwordmem()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.h52 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
57 void printOperand(const MCInst *MI, int OpNum, raw_ostream &O);
62 void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
67 void printU1ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
68 void printU2ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
69 void printU3ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
70 void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
71 void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
72 void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
73 void printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dload.ll31 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
43 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
96 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
124 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
194 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
206 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
259 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
287 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
358 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
423 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
H A Dstore.ll30 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
42 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
95 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
164 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
176 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
229 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
298 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
363 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
529 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
679 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
H A Darith-fp.ll8 ; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32
9 ; MIPS32FP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64
10 ; MM: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32_MM
11 ; MMFP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM
18 ; MIPS32: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32
19 ; MIPS32FP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64
28 ; MIPS32: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32
29 ; MIPS32FP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64
38 ; MIPS32: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32
39 ; MIPS32FP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dvalid.s5 # CHECK: # <MCInst #{{.*}} ADDIUSP_MM
7 # CHECK: # <MCInst #{{.*}} ADDIUSP_MM
9 # CHECK: # <MCInst #{{.*}} ADDIUSP_MM
11 # CHECK: # <MCInst #{{.*}} ADDIUSP_MM
13 # CHECK: # <MCInst #{{.*}} ADDIUSP_MM
15 # CHECK: # <MCInst #{{.*}} ANDI16_MM
17 # CHECK: # <MCInst #{{.*}} JRADDIUSP
19 # CHECK: # <MCInst #{{.*}} ADDU16_MM
23 # CHECK: # <MCInst #{{.*}} AND16_MM
25 # CHECK: # <MCInst #{{.*}} NOT16_MM
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.h27 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
29 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
32 void printMemRiOperand(const MCInst *MI, int OpNo, raw_ostream &O,
34 void printMemRrOperand(const MCInst *MI, int OpNo, raw_ostream &O,
36 void printMemSplsOperand(const MCInst *MI, int OpNo, raw_ostream &O,
38 void printCCOperand(const MCInst *MI, int OpNo, raw_ostream &O);
48 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
55 bool printAlias(const MCInst *MI, raw_ostream &Ostream);
56 bool printInst(const MCInst *MI, raw_ostream &Ostream, StringRef Alias,
58 bool printMemoryLoadIncrement(const MCInst *MI, raw_ostream &Ostream,
[all …]

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