Lines Matching refs:MCInst
8 ; MIPS32: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32
9 ; MIPS32FP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64
10 ; MM: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D32_MM
11 ; MMFP64: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM
12 ; MMR6: add.d {{.*}} # <MCInst #{{[0-9]+}} FADD_D64_MM
18 ; MIPS32: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32
19 ; MIPS32FP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64
20 ; MM: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D32_MM
21 ; MMFP64: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM
22 ; MMR6: sub.d {{.*}} # <MCInst #{{[0-9]+}} FSUB_D64_MM
28 ; MIPS32: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32
29 ; MIPS32FP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64
30 ; MM: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D32_MM
31 ; MMFP64: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM
32 ; MMR6: mul.d {{.*}} # <MCInst #{{[0-9]+}} FMUL_D64_MM
38 ; MIPS32: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32
39 ; MIPS32FP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64
40 ; MM: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D32_MM
41 ; MMFP64: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM
42 ; MMR6: div.d {{.*}} # <MCInst #{{[0-9]+}} FDIV_D64_MM
48 ; MIPS32: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32
49 ; MIPS32FP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64
50 ; MM: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D32_MM
51 ; MMFP64: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM
52 ; MMR6: neg.d {{.*}} # <MCInst #{{[0-9]+}} FNEG_D64_MM