Lines Matching refs:MCInst
27 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
30 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
32 ; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
39 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
42 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
44 ; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
51 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
54 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
57 ; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
64 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
67 ; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
71 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
76 ; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
79 ; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
83 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
87 ; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
91 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
95 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
97 ; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
104 ; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
107 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
111 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
115 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
119 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
123 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
126 ; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
133 ; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
136 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
138 ; MMR5FP64-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
145 ; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
148 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
150 ; MIPS32R5FP643-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
161 ; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
164 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
166 ; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
173 ; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
176 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
178 ; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
185 ; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
188 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
191 ; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
198 ; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
201 ; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
205 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
210 ; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
213 ; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
217 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
221 ; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
225 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
229 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
231 ; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
238 ; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
241 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
245 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
249 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
253 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
257 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
260 ; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
267 ; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
270 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
272 ; MMR5FP64-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
279 ; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
282 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
284 ; MIPS32R5FP643-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
295 ; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
298 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
300 ; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
307 ; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
310 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
312 ; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
319 ; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
322 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
325 ; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
332 ; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
335 ; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
339 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
344 ; MIPS4-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
347 ; MIPS4-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
351 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
355 ; MIPS4-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
359 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
363 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
365 ; MIPS4-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
372 ; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
375 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
379 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
383 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
387 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
391 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
394 ; MIPS64R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW64
401 ; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
404 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
406 ; MMR5FP64-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
413 ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
416 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
418 ; MIPS32R5FP643-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
429 ; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
432 ; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
436 ; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
440 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
442 ; MIPS32-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
449 ; MMR3-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
452 ; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
456 ; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
460 ; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
464 ; MMR3-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
469 ; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
472 ; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
476 ; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
480 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
483 ; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
490 ; MMR6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
493 ; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
497 ; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
501 ; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
505 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
510 ; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
513 ; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
517 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
521 ; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
525 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
529 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
531 ; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
538 ; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
541 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
545 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
549 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
553 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
557 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
560 ; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
567 ; MMR5FP64-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi_MM
570 ; MMR5FP64-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
574 ; MMR5FP64-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu_MM
578 ; MMR5FP64-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
582 ; MMR5FP64-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
587 ; MIPS32R5FP643-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
590 ; MIPS32R5FP643-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
594 ; MIPS32R5FP643-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
598 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
600 ; MIPS32R5FP643-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
611 ; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
614 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
616 ; MIPS32-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
623 ; MMR3-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
626 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
628 ; MMR3-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
635 ; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
638 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
641 ; MIPS32R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
648 ; MMR6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
651 ; MMR6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
655 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
660 ; MIPS4-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
663 ; MIPS4-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
667 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
671 ; MIPS4-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
675 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
679 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
681 ; MIPS4-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
688 ; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
691 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
695 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
699 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
703 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
707 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
710 ; MIPS64R6-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
717 ; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
720 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
722 ; MMR5FP64-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1_MM
729 ; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
732 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
734 ; MIPS32R5FP643-NEXT: swc1 $f12, %lo(e)($1) # <MCInst #{{[0-9]+}} SWC1
745 ; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
748 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
750 ; MIPS32-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1
757 ; MMR3-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
760 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
762 ; MMR3-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D32
769 ; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
772 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
775 ; MIPS32R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
782 ; MMR6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
785 ; MMR6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_D64_MMR6
789 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
794 ; MIPS4-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
797 ; MIPS4-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
801 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
805 ; MIPS4-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
809 ; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
813 ; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
815 ; MIPS4-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
822 ; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
825 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
829 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
833 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
837 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
841 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
844 ; MIPS64R6-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164
851 ; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
854 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
856 ; MMR5FP64-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC1_MM_D64
863 ; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
866 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
868 ; MIPS32R5FP643-NEXT: sdc1 $f12, %lo(f)($1) # <MCInst #{{[0-9]+}} SDC164