Lines Matching refs:MCInst
28 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
31 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
33 ; MIPS32-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
40 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
43 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
45 ; MMR3-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
52 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
55 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
58 ; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
65 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
68 ; MMR6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
72 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
77 ; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
80 ; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
84 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
88 ; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
92 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
96 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
98 ; MIPS3-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
105 ; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
108 ; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
112 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
116 ; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
120 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
124 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
126 ; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
133 ; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
136 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
140 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
144 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
148 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
152 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
155 ; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
162 ; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
165 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
167 ; MMR5FP64-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
174 ; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
177 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
179 ; MIPS32R5FP643-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
191 ; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
194 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
196 ; MIPS32-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
203 ; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
206 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
208 ; MMR3-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
215 ; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
218 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
221 ; MIPS32R6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
228 ; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
231 ; MMR6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
235 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
240 ; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
243 ; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
247 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
251 ; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
255 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
259 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
261 ; MIPS3-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
268 ; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
271 ; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
275 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
279 ; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
283 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
287 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
289 ; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
296 ; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
299 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
303 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
307 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
311 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
315 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
318 ; MIPS64R6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
325 ; MMR5FP64-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi_MM
328 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
330 ; MMR5FP64-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
337 ; MIPS32R5FP643-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
340 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
342 ; MIPS32R5FP643-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
355 ; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
358 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
360 ; MIPS32-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
367 ; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
370 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
372 ; MMR3-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
379 ; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
382 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
385 ; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
392 ; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
395 ; MMR6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
399 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
404 ; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
407 ; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
411 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
415 ; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
419 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
423 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
425 ; MIPS3-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
432 ; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
435 ; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
439 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
443 ; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
447 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
451 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
453 ; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
460 ; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
463 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
467 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
471 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
475 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
479 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
482 ; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
489 ; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
492 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
494 ; MMR5FP64-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
501 ; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
504 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
506 ; MIPS32R5FP643-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
518 ; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
521 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
523 ; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
530 ; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
533 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
535 ; MMR3-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
542 ; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
545 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
548 ; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
555 ; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
558 ; MMR6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
562 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
567 ; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
570 ; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
574 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
578 ; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
582 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
586 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
588 ; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
595 ; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
598 ; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
602 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
606 ; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
610 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
614 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
616 ; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
623 ; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
626 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
630 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
634 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
638 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
642 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
645 ; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
652 ; MMR5FP64-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi_MM
655 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
657 ; MMR5FP64-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
664 ; MIPS32R5FP643-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
667 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
669 ; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
682 ; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
685 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
687 ; MIPS32-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
694 ; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
697 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
699 ; MMR3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
706 ; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
709 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
712 ; MIPS32R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
719 ; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
722 ; MMR6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
726 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
731 ; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
734 ; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
738 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
742 ; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
746 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
750 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
752 ; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
759 ; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
762 ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
766 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
770 ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
774 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
778 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
780 ; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
787 ; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
790 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
794 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
798 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
802 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
806 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
809 ; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
816 ; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
819 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
821 ; MMR5FP64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
828 ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
831 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
833 ; MIPS32R5FP643-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
845 ; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
848 ; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
852 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
854 ; MIPS32-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
861 ; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
864 ; MMR3-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
867 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
869 ; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
876 ; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
879 ; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
883 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
886 ; MIPS32R6-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
893 ; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
896 ; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
900 ; MMR6-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
903 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
908 ; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
911 ; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
915 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
919 ; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
923 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
927 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
929 ; MIPS3-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
936 ; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
939 ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
943 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
947 ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
951 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
955 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
957 ; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
964 ; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
967 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
971 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
975 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
979 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
983 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
986 ; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
993 ; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
996 ; MMR5FP64-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
999 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
1001 ; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1008 ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1011 ; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1015 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1017 ; MIPS32R5FP643-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
1030 ; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1033 ; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1037 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1039 ; MIPS32-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
1046 ; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
1049 ; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1053 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
1055 ; MMR3-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
1062 ; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1065 ; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1069 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
1072 ; MIPS32R6-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
1079 ; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
1082 ; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1086 ; MMR6-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
1090 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
1095 ; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
1098 ; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
1102 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1106 ; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
1110 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1114 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1116 ; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
1123 ; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
1126 ; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
1130 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1134 ; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
1138 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1142 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1144 ; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
1151 ; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
1154 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
1158 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1162 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
1166 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1170 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
1173 ; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
1180 ; MMR5FP64-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi_MM
1183 ; MMR5FP64-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
1187 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
1189 ; MMR5FP64-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
1196 ; MIPS32R5FP643-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
1199 ; MIPS32R5FP643-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
1203 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1205 ; MIPS32R5FP643-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
1218 ; MIPS32-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
1221 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1223 ; MIPS32-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1230 ; MMR3-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
1233 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
1235 ; MMR3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
1242 ; MIPS32R6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
1245 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
1248 ; MIPS32R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1255 ; MMR6-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
1258 ; MMR6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
1262 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
1267 ; MIPS3-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
1270 ; MIPS3-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
1274 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1278 ; MIPS3-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
1282 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1286 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1288 ; MIPS3-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1295 ; MIPS64-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
1298 ; MIPS64-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
1302 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1306 ; MIPS64-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
1310 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1314 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1316 ; MIPS64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1323 ; MIPS64R6-NEXT: lui $1, %highest(e) # <MCInst #{{[0-9]+}} LUi64
1326 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(e) # <MCInst #{{[0-9]+}} DADDiu
1330 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1334 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(e) # <MCInst #{{[0-9]+}} DADDiu
1338 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1342 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
1345 ; MIPS64R6-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1352 ; MMR5FP64-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi_MM
1355 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
1357 ; MMR5FP64-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1_MM
1364 ; MIPS32R5FP643-NEXT: lui $1, %hi(e) # <MCInst #{{[0-9]+}} LUi
1367 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1369 ; MIPS32R5FP643-NEXT: lwc1 $f0, %lo(e)($1) # <MCInst #{{[0-9]+}} LWC1
1381 ; MIPS32-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
1384 ; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1386 ; MIPS32-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1
1393 ; MMR3-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
1396 ; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
1398 ; MMR3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D32
1405 ; MIPS32R6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
1408 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
1411 ; MIPS32R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1418 ; MMR6-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
1421 ; MMR6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_D64_MMR6
1425 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
1430 ; MIPS3-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
1433 ; MIPS3-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
1437 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1441 ; MIPS3-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
1445 ; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1449 ; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1451 ; MIPS3-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1458 ; MIPS64-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
1461 ; MIPS64-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
1465 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1469 ; MIPS64-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
1473 ; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1477 ; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1479 ; MIPS64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1486 ; MIPS64R6-NEXT: lui $1, %highest(f) # <MCInst #{{[0-9]+}} LUi64
1489 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(f) # <MCInst #{{[0-9]+}} DADDiu
1493 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1497 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(f) # <MCInst #{{[0-9]+}} DADDiu
1501 ; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
1505 ; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
1508 ; MIPS64R6-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164
1515 ; MMR5FP64-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi_MM
1518 ; MMR5FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
1520 ; MMR5FP64-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC1_MM_D64
1527 ; MIPS32R5FP643-NEXT: lui $1, %hi(f) # <MCInst #{{[0-9]+}} LUi
1530 ; MIPS32R5FP643-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
1532 ; MIPS32R5FP643-NEXT: ldc1 $f0, %lo(f)($1) # <MCInst #{{[0-9]+}} LDC164