Home
last modified time | relevance | path

Searched refs:LoadVT (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4759 if (!LoadVT.isVector()) in adjustLoadValueTypeImpl()
4765 EVT FittingLoadVT = LoadVT; in adjustLoadValueTypeImpl()
4805 EVT LoadVT = M->getValueType(0); in adjustLoadValueType() local
4807 EVT EquivLoadVT = LoadVT; in adjustLoadValueType()
4808 if (LoadVT.isVector()) { in adjustLoadValueType()
4838 EVT LoadVT = M->getValueType(0); in lowerIntrinsicLoad() local
4855 if (isTypeLegal(LoadVT)) { in lowerIntrinsicLoad()
6399 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) || in lowerImage()
6711 MVT LoadVT = VT.getSimpleVT(); in lowerSBuffer() local
6712 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1; in lowerSBuffer()
[all …]
H A DSIISelLowering.h252 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h572 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
577 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) in isLoadBitCastBeneficial()
580 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial()
2731 EVT LoadVT = getValueType(DL, Load->getType()); in isExtLoad() local
2735 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) && in isExtLoad()
2748 return isLoadExtLegal(LType, VT, LoadVT); in isExtLoad()
H A DBasicTTIImpl.h979 EVT LoadVT = EVT::getEVT(Src);
983 TLI->isLoadExtLegal(LType, ExtVT, LoadVT))
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DStatepointLowering.cpp1300 auto LoadVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitGCRelocate() local
1304 DAG.getLoad(LoadVT, getCurSDLoc(), Chain, SpillSlot, LoadMMO); in visitGCRelocate()
H A DSelectionDAGBuilder.cpp7851 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, in getMemCmpLoad() argument
7859 if (LoadVT.isVector()) in getMemCmpLoad()
7887 Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, Ptr, in getMemCmpLoad()
7965 MVT LoadVT; in visitMemCmpBCmpCall() local
7971 LoadVT = MVT::i16; in visitMemCmpBCmpCall()
7974 LoadVT = MVT::i32; in visitMemCmpBCmpCall()
7979 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare); in visitMemCmpBCmpCall()
7983 if (LoadVT == MVT::INVALID_SIMPLE_VALUE_TYPE) in visitMemCmpBCmpCall()
7986 SDValue LoadL = getMemCmpLoad(LHS, LoadVT, *this); in visitMemCmpBCmpCall()
7987 SDValue LoadR = getMemCmpLoad(RHS, LoadVT, *this); in visitMemCmpBCmpCall()
[all …]
H A DLegalizeDAG.cpp880 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps() local
882 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
886 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType; in LegalizeLoadOps()
888 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr, in LegalizeLoadOps()
H A DTargetLowering.cpp8223 EVT LoadVT = EVT::getIntegerVT(*DAG.getContext(), NumLoadBits); in scalarizeVectorLoad() local
8230 APInt::getLowBitsSet(NumLoadBits, SrcEltBits), SL, LoadVT); in scalarizeVectorLoad()
8235 DAG.getExtLoad(ISD::EXTLOAD, SL, LoadVT, Chain, BasePTR, in scalarizeVectorLoad()
8245 LoadVT, SL, /*LegalTypes=*/false); in scalarizeVectorLoad()
8246 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
8248 DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask); in scalarizeVectorLoad()
H A DDAGCombiner.cpp6180 EVT LoadVT = MLoad->getMemoryVT(); in visitAND() local
6182 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) { in visitAND()
6187 LoadVT.getVectorElementType().getScalarSizeInBits(); in visitAND()
6192 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(), in visitAND()
18072 EVT LoadVT; in getStoreMergeCandidates() local
18076 LoadVT = Ld->getMemoryVT(); in getStoreMergeCandidates()
18078 if (MemVT != LoadVT) in getStoreMergeCandidates()
18110 if (LoadVT != OtherLd->getMemoryVT()) in getStoreMergeCandidates()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2579 EVT LoadVT = EltVT; in LowerFormalArguments() local
2581 LoadVT = MVT::i8; in LowerFormalArguments()
2586 LoadVT = MVT::i32; in LowerFormalArguments()
2588 EVT VecVT = EVT::getVectorVT(F->getContext(), LoadVT, NumElts); in LowerFormalArguments()
2602 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
2621 LoadVT.getFixedSizeInBits()) { in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1390 bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
H A DX86ISelLowering.cpp5850 bool X86TargetLowering::isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, in isLoadBitCastBeneficial() argument
5853 if (!Subtarget.hasAVX512() && !LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
5857 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8) in isLoadBitCastBeneficial()
5861 if (LoadVT.isVector() && BitcastVT.isVector() && in isLoadBitCastBeneficial()
5862 isTypeLegal(LoadVT) && isTypeLegal(BitcastVT)) in isLoadBitCastBeneficial()
42718 LoadVT = MVT::getVectorVT(LoadVT, SrcVT.getVectorNumElements()); in combineBitcast()
42720 SDVTList Tys = DAG.getVTList(LoadVT, MVT::Other); in combineBitcast()
51196 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineX86INT_TO_FP() local
51197 if (SDValue VZLoad = narrowLoadToVZLoad(LN, MemVT, LoadVT, DAG)) { in combineX86INT_TO_FP()
51225 MVT LoadVT = MVT::getVectorVT(MemVT, 128 / NumBits); in combineCVTP2I_CVTTP2I() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16922 EVT LoadVT = VT; in performLDNT1Combine() local
16924 LoadVT = VT.changeTypeToInteger(); in performLDNT1Combine()
16927 SDValue PassThru = DAG.getConstant(0, DL, LoadVT); in performLDNT1Combine()
16928 SDValue L = DAG.getMaskedLoad(LoadVT, DL, MINode->getChain(), in performLDNT1Combine()
16950 EVT LoadVT = VT; in performLD1ReplicateCombine() local
16952 LoadVT = VT.changeTypeToInteger(); in performLD1ReplicateCombine()
16955 SDValue Load = DAG.getNode(Opcode, DL, {LoadVT, MVT::Other}, Ops); in performLD1ReplicateCombine()
20988 EVT LoadVT = ContainerVT; in LowerFixedLengthVectorLoadToSVE() local
20994 LoadVT = ContainerVT.changeTypeToInteger(); in LowerFixedLengthVectorLoadToSVE()
20999 LoadVT, DL, Load->getChain(), Load->getBasePtr(), Load->getOffset(), Pg, in LowerFixedLengthVectorLoadToSVE()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp6802 EVT LoadVT = N->getValueType(0); in combineBSWAP() local
6803 if (LoadVT == MVT::i16) in combineBSWAP()
6804 LoadVT = MVT::i32; in combineBSWAP()
6807 DAG.getVTList(LoadVT, MVT::Other), in combineBSWAP()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15247 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine() local
15249 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
15250 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp15857 EVT LoadVT = isLaneOp ? VecTy.getVectorElementType() : AlignedVecTy; in TryCombineBaseUpdate() local
15858 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys, Ops, LoadVT, in TryCombineBaseUpdate()
18555 EVT LoadVT = N->getOperand(0).getValueType().getHalfNumVectorElementsVT( in PerformMVEExtCombine() local
18558 LoadVT = LoadVT.getHalfNumVectorElementsVT(*DAG.getContext()); in PerformMVEExtCombine()
18574 VT, Chain, Ptr, MPI, LoadVT, Align(4)); in PerformMVEExtCombine()