Home
last modified time | relevance | path

Searched refs:LegalOperations (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1345 if (!LegalOperations) in PromoteIntBinOp()
1413 if (!LegalOperations) in PromoteIntShiftOp()
1462 if (!LegalOperations) in PromoteExtend()
1490 if (!LegalOperations) in PromoteLoad()
5677 if (LegalOperations && in isAndLoadExtLoad()
6521 if (!LegalOperations) in MatchBSwapHWordLow()
6791 if (!LegalOperations) in MatchBSwapHWord()
8232 if (LegalOperations && in MatchLoadCombine()
20734 if (LegalOperations) in convertBuildVecZextToZext()
21559 if (LegalOperations && in foldExtractSubvectorFromShuffleVector()
[all …]
H A DTargetLowering.cpp2056 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SHL, VT)) && in SimplifyDemandedBits()
2061 if ((!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT)) && in SimplifyDemandedBits()
2131 if (!TLO.LegalOperations() || isOperationLegal(ShiftOpcode, VT)) { in SimplifyDemandedBits()
2253 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
2290 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
2314 if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) in SimplifyDemandedBits()
2473 if (!TLO.LegalOperations() && !VT.isVector() && !SrcVT.isVector() && in SimplifyDemandedBits()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.h58 bool LegalOperations) const override { in canCombineTruncStore() argument
H A DAMDGPUISelLowering.h170 bool LegalOperations, bool ForCodeSize,
H A DAMDGPUISelLowering.cpp730 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, in getNegatedExpression() argument
745 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1016 bool LegalOperations, bool ForCodeSize,
H A DX86ISelLowering.cpp50774 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFneg() local
50776 TLI.getNegatedExpression(Arg, DAG, LegalOperations, CodeSize)) in combineFneg()
50783 bool LegalOperations, in getNegatedExpression() argument
50821 Op.getOperand(i), DAG, LegalOperations, ForCodeSize, Depth + 1); in getNegatedExpression()
50839 getNegatedExpression(Op.getOperand(0), DAG, LegalOperations, in getNegatedExpression()
50845 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
51751 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMA() local
51752 if (SDValue NegV = TLI.getCheaperNegatedExpression(V, DAG, LegalOperations, in combineFMA()
51763 Vec, DAG, LegalOperations, CodeSize)) { in combineFMA()
51806 bool LegalOperations = !DCI.isBeforeLegalizeOps(); in combineFMADDSUB() local
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3551 bool LegalOperations() const { return LegalOps; } in LegalOperations() function