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Searched refs:LHS1 (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dreduction-or-sext-zext-i1.ll104 ; CHECK-NEXT: [[LHS1:%.*]] = load i64, i64* [[TMP0]], align 8
107 ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i64 [[LHS1]], [[RHS2]]
149 ; CHECK-NEXT: [[LHS1:%.*]] = load i64, i64* [[TMP0]], align 8
152 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[LHS1]], [[RHS2]]
H A Dreduction-and-sext-zext-i1.ll104 ; CHECK-NEXT: [[LHS1:%.*]] = load i64, i64* [[TMP0]], align 8
107 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[LHS1]], [[RHS2]]
146 ; CHECK-NEXT: [[LHS1:%.*]] = load i64, i64* [[TMP0]], align 8
149 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[LHS1]], [[RHS2]]
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp1214 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1234 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
1246 return getFCmpValue(NewPred, LHS0, LHS1, Builder); in foldLogicOfFCmps()
2531 match(LHS1, m_APInt(LHSC)); in foldAndOrOfICmps()
2537 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldAndOrOfICmps()
2539 std::swap(LHS0, LHS1); in foldAndOrOfICmps()
2541 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldAndOrOfICmps()
3190 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldXorOfICmps()
3191 std::swap(LHS0, LHS1); in foldXorOfICmps()
3194 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldXorOfICmps()
[all …]
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DInstructionSimplify.cpp1946 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in simplifyAndOrOfFCmps() local
1962 if ((isKnownNeverNaN(LHS0, TLI) && (LHS1 == RHS0 || LHS1 == RHS1)) || in simplifyAndOrOfFCmps()
1963 (isKnownNeverNaN(LHS1, TLI) && (LHS0 == RHS0 || LHS0 == RHS1))) in simplifyAndOrOfFCmps()
1974 if ((isKnownNeverNaN(RHS0, TLI) && (RHS1 == LHS0 || RHS1 == LHS1)) || in simplifyAndOrOfFCmps()
1975 (isKnownNeverNaN(RHS1, TLI) && (RHS0 == LHS0 || RHS0 == LHS1))) in simplifyAndOrOfFCmps()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp720 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp() local
748 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); in getAVRCmp()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5638 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
5640 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
5647 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
11993 Register LHS1 = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
11997 .addReg(LHS1) in EmitInstrWithCustomInserter()
12007 .addReg(LHS1) in EmitInstrWithCustomInserter()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp24147 SDValue LHS1, LHS2; in splitIntVSETCC() local
24148 std::tie(LHS1, LHS2) = splitVector(LHS, DAG, dl); in splitIntVSETCC()
24158 DAG.getNode(ISD::SETCC, dl, LoVT, LHS1, RHS1, CC), in splitIntVSETCC()
47026 SDValue LHS1 = LHS.getOperand(1); in combineVectorHADDSUB() local
47029 if ((LHS0 == LHS1 || LHS0.isUndef() || LHS1.isUndef()) && in combineVectorHADDSUB()
47033 LHS0.isUndef() ? LHS1 : LHS0, in combineVectorHADDSUB()