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Searched refs:LHS0 (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp1214 if (LHS0 == RHS1 && RHS0 == LHS1) { in foldLogicOfFCmps()
1234 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldLogicOfFCmps()
2493 Value *LHS0 = LHS->getOperand(0); in foldAndOrOfICmpEqZeroAndICmp() local
2509 Builder.CreateAdd(LHS0, Constant::getAllOnesValue(LHS0->getType())), in foldAndOrOfICmpEqZeroAndICmp()
2537 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldAndOrOfICmps()
2539 std::swap(LHS0, LHS1); in foldAndOrOfICmps()
2541 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldAndOrOfICmps()
3190 if (LHS0 == RHS1 && LHS1 == RHS0) { in foldXorOfICmps()
3191 std::swap(LHS0, LHS1); in foldXorOfICmps()
3194 if (LHS0 == RHS0 && LHS1 == RHS1) { in foldXorOfICmps()
[all …]
/llvm-project-15.0.7/mlir/test/Integration/Dialect/Async/CPU/
H A Dmicrobench-linalg-async-parallel-for.mlir97 %LHS0 = memref.cast %LHS1024 : memref<1024x1024xf32> to memref<?x?xf32>
105 call @linalg_generic(%LHS0, %RHS0, %DST0)
114 func.call @linalg_generic(%LHS0, %RHS0, %DST0)
H A Dmicrobench-scf-async-parallel-for.mlir119 %LHS0 = memref.cast %LHS1024 : memref<1024x1024xf32> to memref<?x?xf32>
127 call @scf_parallel(%LHS0, %RHS0, %DST0)
136 func.call @scf_parallel(%LHS0, %RHS0, %DST0)
/llvm-project-15.0.7/mlir/test/Interfaces/TilingInterface/
H A Dtile-and-fuse-using-interface.mlir105 // CHECK-SAME: %[[LHS0:[a-zA-Z0-9]+]]: tensor<?x?xf32>
110 // CHECK-DAG: %[[D0:.+]] = tensor.dim %[[LHS0]], %[[C0]]
117 // CHECK-DAG: %[[LHS0_TILE:.+]] = tensor.extract_slice %[[LHS0]][%[[IV]], 0]
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DInstructionSimplify.cpp1946 Value *LHS0 = LHS->getOperand(0), *LHS1 = LHS->getOperand(1); in simplifyAndOrOfFCmps() local
1948 if (LHS0->getType() != RHS0->getType()) in simplifyAndOrOfFCmps()
1962 if ((isKnownNeverNaN(LHS0, TLI) && (LHS1 == RHS0 || LHS1 == RHS1)) || in simplifyAndOrOfFCmps()
1963 (isKnownNeverNaN(LHS1, TLI) && (LHS0 == RHS0 || LHS0 == RHS1))) in simplifyAndOrOfFCmps()
1974 if ((isKnownNeverNaN(RHS0, TLI) && (RHS1 == LHS0 || RHS1 == LHS1)) || in simplifyAndOrOfFCmps()
1975 (isKnownNeverNaN(RHS1, TLI) && (RHS0 == LHS0 || RHS0 == LHS1))) in simplifyAndOrOfFCmps()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp718 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, in getAVRCmp() local
747 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); in getAVRCmp()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp8786 SDValue LHS0 = LHS.getOperand(0); in combine_CC() local
8787 if (LHS0.getOpcode() == ISD::AND && in combine_CC()
8788 LHS0.getOperand(1).getOpcode() == ISD::Constant) { in combine_CC()
8789 uint64_t Mask = LHS0.getConstantOperandVal(1); in combine_CC()
8796 LHS = LHS0.getOperand(0); in combine_CC()
8799 DAG.getNode(ISD::SHL, DL, LHS.getValueType(), LHS0.getOperand(0), in combine_CC()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp47025 SDValue LHS0 = LHS.getOperand(0); in combineVectorHADDSUB() local
47029 if ((LHS0 == LHS1 || LHS0.isUndef() || LHS1.isUndef()) && in combineVectorHADDSUB()
47033 LHS0.isUndef() ? LHS1 : LHS0, in combineVectorHADDSUB()