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Searched refs:LH (Results 1 – 25 of 50) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp510 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_Select() local
513 GetSplitOp(N->getOperand(1), LL, LH); in SplitRes_Select()
545 Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH); in SplitRes_Select()
554 Hi = DAG.getNode(Opcode, dl, LH.getValueType(), CH, LH, RH, EVLHi); in SplitRes_Select()
559 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
561 GetSplitOp(N->getOperand(2), LL, LH); in SplitRes_SELECT_CC()
566 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
567 N->getOperand(1), LH, RH, N->getOperand(4)); in SplitRes_SELECT_CC()
H A DTargetLowering.cpp7020 if (!LH.getNode() && !RH.getNode() && in expandMUL_LOHI()
7023 LH = DAG.getNode(ISD::SRL, dl, VT, LHS, Shift); in expandMUL_LOHI()
7024 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH); in expandMUL_LOHI()
7029 if (!LH.getNode()) in expandMUL_LOHI()
7039 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL); in expandMUL_LOHI()
7041 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH); in expandMUL_LOHI()
7062 if (!MakeMUL_LOHI(LH, RL, Lo, Hi, false)) in expandMUL_LOHI()
7081 if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI)) in expandMUL_LOHI()
7096 Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT); in expandMUL_LOHI()
7111 SDValue LL, SDValue LH, SDValue RL, in expandMUL() argument
[all …]
H A DLegalizeIntegerTypes.cpp3636 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
3637 GetExpandedInteger(N->getOperand(0), LL, LH); in ExpandIntRes_Logical()
3640 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); in ExpandIntRes_Logical()
3649 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
3650 GetExpandedInteger(N->getOperand(0), LL, LH); in ExpandIntRes_MUL()
3655 LL, LH, RL, RH)) in ExpandIntRes_MUL()
3707 DAG.getNode(ISD::MUL, dl, NVT, RL, LH))); in ExpandIntRes_MUL()
3799 SDValue LL, LH, RL, RH; in ExpandIntRes_MULFIX() local
3800 GetExpandedInteger(LHS, LL, LH); in ExpandIntRes_MULFIX()
3807 LL, LH, RL, RH)) { in ExpandIntRes_MULFIX()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A DzextLoad_and_sextLoad.mir90 ; MIPS32: [[LH:%[0-9]+]]:gpr32 = LH [[COPY]], 0 :: (load (s16) from %ir.px)
91 ; MIPS32: $v0 = COPY [[LH]]
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaStmtAttr.cpp326 const LoopHintAttr *LH = dyn_cast<LoopHintAttr>(I); in CheckForIncompatibleAttributes() local
329 if (!LH) in CheckForIncompatibleAttributes()
332 LoopHintAttr::OptionType Option = LH->getOption(); in CheckForIncompatibleAttributes()
383 CategoryState.StateAttr = LH; in CheckForIncompatibleAttributes()
387 CategoryState.NumericAttr = LH; in CheckForIncompatibleAttributes()
391 SourceLocation OptionLoc = LH->getRange().getBegin(); in CheckForIncompatibleAttributes()
396 << LH->getDiagnosticName(Policy); in CheckForIncompatibleAttributes()
H A DSemaTemplateInstantiate.cpp1094 const LoopHintAttr *TransformLoopHintAttr(const LoopHintAttr *LH);
1502 TemplateInstantiator::TransformLoopHintAttr(const LoopHintAttr *LH) { in TransformLoopHintAttr() argument
1503 Expr *TransformedExpr = getDerived().TransformExpr(LH->getValue()).get(); in TransformLoopHintAttr()
1505 if (TransformedExpr == LH->getValue()) in TransformLoopHintAttr()
1506 return LH; in TransformLoopHintAttr()
1509 if (getSema().CheckLoopHintExpr(TransformedExpr, LH->getLocation())) in TransformLoopHintAttr()
1510 return LH; in TransformLoopHintAttr()
1514 return LoopHintAttr::CreateImplicit(getSema().Context, LH->getOption(), in TransformLoopHintAttr()
1515 LH->getState(), TransformedExpr, *LH); in TransformLoopHintAttr()
/llvm-project-15.0.7/llvm/test/tools/llvm-cov/
H A DshowLineExecutionCounts-lcov.test27 // FULL: LH:18
37 // SUMMARYONLY: LH:18
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-conv-05.ll25 ; Check the low end of the LH range.
35 ; Check the high end of the LH range.
46 ; Check the next halfword up, which needs LHY rather than LH.
116 ; Check that LH allows an index
129 ; Check that LH allows an index
143 ; to use LH if possible.
H A Dbranch-folder-hoist-livein.mir23 …renamable $r1l = LH killed renamable $r1d, 0, $noreg, implicit-def $r1d :: (dereferenceable load (…
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCodeGenFunction.cpp1658 EmitBranchOnBoolExpr(Cond, ThenBlock, ElseBlock, TrueCount, LH); in EmitBranchToCounterBlock()
1678 Stmt::Likelihood LH) { in EmitBranchOnBoolExpr() argument
1719 LH == Stmt::LH_Unlikely ? Stmt::LH_None : LH); in EmitBranchOnBoolExpr()
1729 FalseBlock, TrueCount, LH); in EmitBranchOnBoolExpr()
1773 LH == Stmt::LH_Likely ? Stmt::LH_None : LH); in EmitBranchOnBoolExpr()
1783 RHSCount, LH); in EmitBranchOnBoolExpr()
1797 LH = static_cast<Stmt::Likelihood>(-LH); in EmitBranchOnBoolExpr()
1800 FalseCount, LH); in EmitBranchOnBoolExpr()
1833 LHSScaledTrueCount, LH); in EmitBranchOnBoolExpr()
1840 TrueCount - LHSScaledTrueCount, LH); in EmitBranchOnBoolExpr()
[all …]
H A DCGLoopInfo.cpp602 const LoopHintAttr *LH = dyn_cast<LoopHintAttr>(Attr); in push() local
607 if (!LH && !OpenCLHint) { in push()
628 } else if (LH) { in push()
629 auto *ValueExpr = LH->getValue(); in push()
635 Option = LH->getOption(); in push()
636 State = LH->getState(); in push()
753 if (LH->getValue()) in push()
H A DCGStmt.cpp818 Stmt::Likelihood LH = Stmt::LH_None; in EmitIfStmt() local
821 LH = Stmt::getLikelihood(S.getThen(), S.getElse()); in EmitIfStmt()
822 EmitBranchOnBoolExpr(S.getCond(), ThenBlock, ElseBlock, Count, LH); in EmitIfStmt()
1425 Stmt::Likelihood LH = Stmt::getLikelihood(Attrs); in EmitCaseStmtRange() local
1441 SwitchLikelihood->push_back(LH); in EmitCaseStmtRange()
1481 Cond = emitCondLikelihoodViaExpectIntrinsic(Cond, LH); in EmitCaseStmtRange()
1870 for (const auto LH : Likelihoods) { in getLikelihoodWeights() local
1871 switch (LH) { in getLikelihoodWeights()
1900 for (const auto LH : Likelihoods) { in getLikelihoodWeights() local
1901 switch (LH) { in getLikelihoodWeights()
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp222 case Mips::LH: in isBasePlusOffsetMemoryAccess()
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dswaps-le-2.ll6 ; LH: 2016-11-17
H A Dswaps-le-1.ll16 ; LH: 2016-11-17
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td159 foreach V = [ "E", "H", "L", "HE", "LE", "LH",
250 foreach V = [ "E", "H", "L", "HE", "LE", "LH",
652 // either way, but signed-extending loads have a short LH and a long LHY,
682 // 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
686 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
706 // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
710 // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
936 // IIxMux expands to II[LH]x, depending on the choice of register.
1190 // NIxMux expands to NI[LH]x, depending on the choice of register.
1248 // OIxMux expands to OI[LH]x, depending on the choice of register.
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp330 case RISCV::LH: in detectAndFoldOffset()
H A DRISCVSExtWRemoval.cpp232 case RISCV::LH: in isSignExtendingOpW()
H A DRISCVInstrInfoA.td116 defm : LdPat<atomic_load_16, LH>;
H A DRISCVInstrInfo.td615 def LH : Load_ri<0b001, "lh">, Sched<[WriteLDH, ReadMemBase]>;
968 (LH GPR:$rd, GPR:$rs1, 0)>;
1465 defm : LdPat<sextloadi16, LH>;
1466 defm : LdPat<extloadi16, LH>;
H A DRISCVInstrInfo.cpp76 case RISCV::LH: in isLoadFromStackSlot()
674 LoadOpc = RISCV::LH; in foldMemoryOperandImpl()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp673 SDValue LH, RH; in TryExpandADDWithMul() local
674 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
683 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); in TryExpandADDWithMul()
685 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); in TryExpandADDWithMul()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dload.ll523 ; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
548 ; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
588 ; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
616 ; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
645 ; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
669 ; MIPS32R5FP643-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp654 case Mips::LH: in HasLoadDelaySlot()
/llvm-project-15.0.7/llvm/docs/
H A DTestSuiteGuide.md145 % cmake -LH

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