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Searched refs:ItinData (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp39 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
41 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
44 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
45 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
73 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
113 if (!ItinData || ItinData->isEmpty()) in getHazardType()
128 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
129 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
172 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
187 for (const InstrStage *IS = ItinData->beginStage(idx), in EmitInstruction()
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H A DTargetInstrInfo.cpp1088 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1091 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1099 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1104 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1106 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1121 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1125 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
1155 if (!ItinData) in getInstrLatency()
1158 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1165 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h315 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
318 int getOperandLatency(const InstrItineraryData *ItinData,
322 int getOperandLatency(const InstrItineraryData *ItinData,
423 int getVLDMDefCycle(const InstrItineraryData *ItinData,
427 int getLDMDefCycle(const InstrItineraryData *ItinData,
431 int getVSTMUseCycle(const InstrItineraryData *ItinData,
435 int getSTMUseCycle(const InstrItineraryData *ItinData,
439 int getOperandLatency(const InstrItineraryData *ItinData,
445 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
454 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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H A DARMBaseInstrInfo.cpp3754 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3759 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3762 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
4361 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
4463 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
4758 if (!ItinData) in getInstrLatency()
4764 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) in getInstrLatency()
4765 return getNumMicroOps(ItinData, MI); in getInstrLatency()
4768 unsigned Latency = ItinData->getStageLatency(Class); in getInstrLatency()
4785 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer() argument
36 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), in PPCDispatchGroupSBHazardRecognizer()
H A DPPCInstrInfo.h409 unsigned getInstrLatency(const InstrItineraryData *ItinData,
413 int getOperandLatency(const InstrItineraryData *ItinData,
417 int getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
420 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
H A DPPCInstrInfo.cpp136 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
139 if (!ItinData || UseOldLatencyCalc) in getInstrLatency()
140 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
156 int Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency()
166 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
170 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
192 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp83 Record *ItinData, std::string &ItinString,
88 Record *ItinData,
331 Record *ItinData, in FormItineraryStageString() argument
335 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
378 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString()
391 Record *ItinData, in FormItineraryBypassString() argument
394 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
493 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
498 if (ItinData) in EmitStageAndOperandCycleData()
506 if (ItinData) { in EmitStageAndOperandCycleData()
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H A DCodeGenSchedule.cpp1169 for (Record *ItinData : ItinRecords) { in collectProcItins()
1170 const Record *ItinDef = ItinData->getValueAsDef("TheClass"); in collectProcItins()
1177 ProcModel.ItinDefList[SC.Index] = ItinData; in collectProcItins()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h94 const InstrItineraryData *ItinData; variable
H A DTargetInstrInfo.h1589 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1600 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1612 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1620 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1626 virtual int getInstrLatency(const InstrItineraryData *ItinData,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h279 unsigned getInstrLatency(const InstrItineraryData *ItinData,
311 int getOperandLatency(const InstrItineraryData *ItinData,
458 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
H A DHexagonInstrInfo.cpp1961 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1964 return getInstrTimingClassLatency(ItinData, MI); in getInstrLatency()
4269 const InstrItineraryData *ItinData, const MachineInstr &MI) const { in getInstrTimingClassLatency() argument
4272 if (!ItinData) in getInstrTimingClassLatency()
4273 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
4277 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency()
4288 int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
4321 int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h207 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
H A DSIInstrInfo.h1166 unsigned getInstrLatency(const InstrItineraryData *ItinData,
H A DR600InstrInfo.cpp983 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
H A DSIInstrInfo.cpp8216 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument