3450 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,  in getNumMicroOpsSwiftLdSt()  argument
3455     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());  in getNumMicroOpsSwiftLdSt()
3752 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()  argument
3754   if (!ItinData || ItinData->isEmpty())  in getNumMicroOps()
3759   int ItinUOps = ItinData->getNumMicroOps(Class);  in getNumMicroOps()
3762       return getNumMicroOpsSwiftLdSt(ItinData, MI);  in getNumMicroOps()
3866 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()  argument
3873     return ItinData->getOperandCycle(DefClass, DefIdx);  in getVLDMDefCycle()
3907 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()  argument
3914     return ItinData->getOperandCycle(DefClass, DefIdx);  in getLDMDefCycle()
3942 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()  argument
3948     return ItinData->getOperandCycle(UseClass, UseIdx);  in getVSTMUseCycle()
3982 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()  argument
3988     return ItinData->getOperandCycle(UseClass, UseIdx);  in getSTMUseCycle()
4011 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
4020     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
4029     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
4038     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4059     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4070     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);  in getOperandLatency()
4079     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
4097     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
4110       if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,  in getOperandLatency()
4113     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,  in getOperandLatency()
4355 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
4361   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
4387       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,  in getOperandLatency()
4392     const InstrItineraryData *ItinData, const MachineInstr &DefMI,  in getOperandLatencyImpl()  argument
4407     unsigned Latency = getInstrLatency(ItinData, DefMI);  in getOperandLatencyImpl()
4433   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,  in getOperandLatencyImpl()
4452 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
4463   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
4467     int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);  in getOperandLatency()
4482   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,  in getOperandLatency()
4729 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4744         Latency += getInstrLatency(ItinData, *I, PredCost);  in getInstrLatency()
4758   if (!ItinData)  in getInstrLatency()
4764   if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)  in getInstrLatency()
4765     return getNumMicroOps(ItinData, MI);  in getInstrLatency()
4768   unsigned Latency = ItinData->getStageLatency(Class);  in getInstrLatency()
4780 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4785   if (!ItinData || ItinData->isEmpty())  in getInstrLatency()
4791     return ItinData->getStageLatency(get(Opcode).getSchedClass());  in getInstrLatency()
4822   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();  in hasLowDefLatency()  local
4823   if (!ItinData || ItinData->isEmpty())  in hasLowDefLatency()
4829     int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()