Lines Matching refs:ItinData
1088 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1091 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1099 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1101 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1104 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1106 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1112 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1119 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1121 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1125 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
1150 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1155 if (!ItinData) in getInstrLatency()
1158 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1164 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); in hasLowDefLatency() local
1165 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
1169 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1256 int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1263 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()