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Searched refs:IsSub (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kFrameLowering.cpp340 bool IsSub = NumBytes < 0; in emitSPUpdate() local
341 uint64_t Offset = IsSub ? -NumBytes : NumBytes; in emitSPUpdate()
352 if (IsSub && !isRegLiveIn(MBB, M68k::D0)) in emitSPUpdate()
360 Opc = IsSub ? M68k::SUB32ar : M68k::ADD32ar; in emitSPUpdate()
374 MBB, MBBI, DL, IsSub ? -ThisVal : ThisVal, InEpilogue); in emitSPUpdate()
375 if (IsSub) in emitSPUpdate()
427 bool IsSub = Offset < 0; in BuildStackAdjustment() local
428 uint64_t AbsOffset = IsSub ? -Offset : Offset; in BuildStackAdjustment()
429 unsigned Opc = IsSub ? M68k::SUB32ai : M68k::ADD32ai; in BuildStackAdjustment()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp587 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters() local
591 if (!IsSub) in FindSuitableFreeRegisters()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1801 bool IsSub = ExtOpc == Hexagon::S4_subaddi; in replaceInstrExpr() local
1802 Register Rs = MI.getOperand(IsSub ? 3 : 2); in replaceInstrExpr()
1803 ExtValue V = MI.getOperand(IsSub ? 2 : 3); in replaceInstrExpr()
1804 assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg && "Initializer mismatch"); in replaceInstrExpr()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp363 bool IsSub = Offset < 0; in BuildStackAdjustment() local
364 uint64_t AbsOffset = IsSub ? -Offset : Offset; in BuildStackAdjustment()
365 const unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset) in BuildStackAdjustment()
H A DX86ISelLowering.cpp52875 (IsSub && CC == X86::COND_B && ConstantX->isZero())) { in combineAddOrSubToADCOrSBB()
52885 (IsSub && CC == X86::COND_A && ConstantX->isZero())) { in combineAddOrSubToADCOrSBB()
52906 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, in combineAddOrSubToADCOrSBB()
52928 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, in combineAddOrSubToADCOrSBB()
52937 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, in combineAddOrSubToADCOrSBB()
52958 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, in combineAddOrSubToADCOrSBB()
52996 if ((IsSub && CC == X86::COND_E && ConstantX->isZero()) || in combineAddOrSubToADCOrSBB()
53031 bool IsSub = N->getOpcode() == ISD::SUB; in combineAddOrSubToADCOrSBB() local
53042 if (IsSub) in combineAddOrSubToADCOrSBB()
53171 bool IsSub = X86ISD::SUB == N->getOpcode(); in combineX86AddSub() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3210 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr || in optimizeCompareInstr() local
3215 if (!IsSub || in optimizeCompareInstr()
3222 ARMCC::CondCodes NewCC = (IsSub ? getSwappedCondition(CC) : getCmpToAddCondition(CC)); in optimizeCompareInstr()
H A DARMISelDAGToDAG.cpp2705 bool IsSub = SDValueToConstBool(N->getOperand(2)); in SelectBaseMVE_VMLLDAV() local
2708 assert(!IsSub && in SelectBaseMVE_VMLLDAV()
2726 if (IsSub) in SelectBaseMVE_VMLLDAV()
/llvm-project-15.0.7/clang/lib/AST/
H A DExprConstant.cpp12585 bool IsSub) { in addOrSubLValueAsInteger() argument
12593 Offset = CharUnits::fromQuantity(IsSub ? Offset64 - Index64 in addOrSubLValueAsInteger()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaChecking.cpp15591 bool IsSub, ASTContext &Ctx) { in getAlignmentAndOffsetFromBinAddOrSub() argument
15605 if (IsSub) in getAlignmentAndOffsetFromBinAddOrSub()