| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 630 bool IsSignaling = false) const;
633 bool IsSignaling) const;
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| H A D | SystemZISelLowering.cpp | 2764 bool IsSignaling = false) { in getCmp() argument
2784 else if (!IsSignaling) in getCmp()
3028 bool IsSignaling) const { in lowerVectorSETCC()
3031 assert (!IsSignaling || Chain); in lowerVectorSETCC()
3032 CmpMode Mode = IsSignaling ? CmpMode::SignalingFP : in lowerVectorSETCC()
3117 bool IsSignaling) const { in lowerSTRICT_FSETCC()
3126 Chain, IsSignaling); in lowerSTRICT_FSETCC()
3130 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL, Chain, IsSignaling)); in lowerSTRICT_FSETCC()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 1834 bool IsSignaling) { in FloatExpandSetCCOperands() argument
1848 RHSHi, ISD::SETOEQ, Chain, IsSignaling); in FloatExpandSetCCOperands()
1851 RHSLo, CCCode, OutputChain, IsSignaling); in FloatExpandSetCCOperands()
1856 ISD::SETUNE, OutputChain, IsSignaling); in FloatExpandSetCCOperands()
1859 RHSHi, CCCode, OutputChain, IsSignaling); in FloatExpandSetCCOperands()
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| H A D | LegalizeTypes.h | 668 SDValue &Chain, bool IsSignaling = false);
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| H A D | TargetLowering.cpp | 304 bool IsSignaling) const { in softenSetCCOperands()
9708 bool IsSignaling) const { in LegalizeSetCCCondCode()
9822 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling); in LegalizeSetCCCondCode()
9823 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling); in LegalizeSetCCCondCode()
9831 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling); in LegalizeSetCCCondCode()
9832 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling); in LegalizeSetCCCondCode()
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| H A D | LegalizeDAG.cpp | 3623 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS; in ExpandNode() local
3636 Chain, IsSignaling); in ExpandNode()
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| /llvm-project-15.0.7/llvm/lib/IR/ |
| H A D | IRBuilder.cpp | 969 MDNode *FPMathTag, bool IsSignaling) { in CreateFCmpHelper() argument
971 auto ID = IsSignaling ? Intrinsic::experimental_constrained_fcmps in CreateFCmpHelper()
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| /llvm-project-15.0.7/llvm/lib/Support/ |
| H A D | APFloat.cpp | 2861 bool IsSignaling = str.front() == 's' || str.front() == 'S'; in convertFromStringSpecials() local
2862 if (IsSignaling) { in convertFromStringSpecials()
2873 makeNaN(IsSignaling, IsNegative); in convertFromStringSpecials()
2899 makeNaN(IsSignaling, IsNegative, &Payload); in convertFromStringSpecials()
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 12818 bool IsSignaling) { in EmitX86BuiltinExpr() argument
12821 if (IsSignaling) in EmitX86BuiltinExpr()
14746 bool IsSignaling; in EmitX86BuiltinExpr() local
14750 case 0x00: Pred = FCmpInst::FCMP_OEQ; IsSignaling = false; break; in EmitX86BuiltinExpr()
14751 case 0x01: Pred = FCmpInst::FCMP_OLT; IsSignaling = true; break; in EmitX86BuiltinExpr()
14752 case 0x02: Pred = FCmpInst::FCMP_OLE; IsSignaling = true; break; in EmitX86BuiltinExpr()
14753 case 0x03: Pred = FCmpInst::FCMP_UNO; IsSignaling = false; break; in EmitX86BuiltinExpr()
14754 case 0x04: Pred = FCmpInst::FCMP_UNE; IsSignaling = false; break; in EmitX86BuiltinExpr()
14771 IsSignaling = !IsSignaling; in EmitX86BuiltinExpr()
14839 if (IsSignaling) in EmitX86BuiltinExpr()
[all …]
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| H A D | CGExprScalar.cpp | 825 llvm::CmpInst::Predicate FCmpOpc, bool IsSignaling);
4076 bool IsSignaling) { in EmitCompare() argument
4172 if (!IsSignaling) in EmitCompare()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1083 bool IsSignaling = false) {
1091 return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
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| H A D | TargetLowering.h | 3514 bool IsSignaling = false) const;
4910 SDValue &Chain, bool IsSignaling = false) const;
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5519 bool IsSignaling = Node->getOpcode() == X86ISD::STRICT_FCMPS; in Select() local
5525 Opc = IsSignaling ? X86::COM_Fpr32 : X86::UCOM_Fpr32; in Select()
5528 Opc = IsSignaling ? X86::COM_Fpr64 : X86::UCOM_Fpr64; in Select()
5531 Opc = IsSignaling ? X86::COM_Fpr80 : X86::UCOM_Fpr80; in Select()
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| H A D | X86ISelLowering.cpp | 24289 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerVSETCC() local
24324 if (IsStrict && IsAlwaysSignaling && !IsSignaling) in LowerVSETCC()
24328 if (IsStrict && !IsAlwaysSignaling && IsSignaling) { in LowerVSETCC()
24388 SSECC |= (IsAlwaysSignaling ^ IsSignaling) << 4; in LowerVSETCC()
24909 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC() local
24911 DAG.getNode(IsSignaling ? X86ISD::STRICT_FCMPS : X86ISD::STRICT_FCMP, in LowerSETCC()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 2210 bool IsSignaling);
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2866 bool IsSignaling) { in emitStrictFPComparison() argument
2881 IsSignaling ? AArch64ISD::STRICT_FCMPE : AArch64ISD::STRICT_FCMP; in emitStrictFPComparison()
8002 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerSETCC() local
8021 IsSignaling); in LowerSETCC()
8051 Cmp = emitStrictFPComparison(LHS, RHS, dl, DAG, Chain, IsSignaling); in LowerSETCC()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10290 bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; in LowerFSETCC() local
10296 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS, Chain, IsSignaling); in LowerFSETCC()
10318 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, IsSignaling); in LowerFSETCC()
10322 Cmp = getVFPCmp(LHS, RHS, DAG, dl, IsSignaling); in LowerFSETCC()
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