| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelect.cpp | 48 char InstructionSelect::ID = 0;
49 INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
56 INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE, in INITIALIZE_PASS_DEPENDENCY()
60 InstructionSelect::InstructionSelect(CodeGenOpt::Level OL) in INITIALIZE_PASS_DEPENDENCY()
66 InstructionSelect::InstructionSelect() in InstructionSelect() function in InstructionSelect
69 void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const { in getAnalysisUsage()
82 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { in runOnMachineFunction()
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| H A D | CMakeLists.txt | 12 InstructionSelect.cpp
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | InstructionSelect.h | 33 class InstructionSelect : public MachineFunctionPass {
52 InstructionSelect(CodeGenOpt::Level OL);
53 InstructionSelect();
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVTargetMachine.cpp | 177 class SPIRVInstructionSelect : public InstructionSelect {
180 return InstructionSelect::getRequiredProperties().reset( in getRequiredProperties()
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| /llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/ |
| H A D | subreg-def-is-not-ssa.mir | 4 # CHECK: MachineFunctionProperties required by InstructionSelect pass are not met by function subre…
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| /llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/CodeGen/GlobalISel/ |
| H A D | BUILD.gn | 25 "InstructionSelect.cpp",
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kTargetMachine.cpp | 184 addPass(new InstructionSelect()); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/llvm/test/CodeGen/MIR/AArch64/ |
| H A D | print-parse-verify-failedISel-property.mir | 12 # 3) MIRPrinter is able to print FailedISel MIR after InstructionSelect pass.
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| /llvm-project-15.0.7/llvm/docs/GlobalISel/ |
| H A D | Pipeline.rst | 12 InstructionSelect
42 :doc:`Instruction Select <InstructionSelect>`
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| H A D | index.rst | 66 InstructionSelect
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| H A D | InstructionSelect.rst | 4 InstructionSelect title
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| H A D | Legalizer.rst | 12 :doc:`InstructionSelect` has to handle it though. It just means that
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetMachine.cpp | 232 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | O0-pipeline.ll | 42 ; CHECK-NEXT: InstructionSelect
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | gisel-commandline-option.ll | 78 ; ENABLED-NEXT: InstructionSelect
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.cpp | 351 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetMachine.cpp | 490 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 507 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.cpp | 617 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetMachine.cpp | 689 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetMachine.cpp | 1261 addPass(new InstructionSelect(getOptLevel())); in addGlobalInstructionSelect()
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| /llvm-project-15.0.7/clang/docs/tools/ |
| H A D | clang-formatted-files.txt | 5112 llvm/include/llvm/CodeGen/GlobalISel/InstructionSelect.h
5861 llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
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