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Searched refs:Instr (Results 1 – 25 of 179) sorted by relevance

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/llvm-project-15.0.7/llvm/tools/llvm-cfi-verify/lib/
H A DFileAnalysis.h78 struct Instr { struct
98 const Instr *getInstruction(uint64_t Address) const;
107 const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const;
108 const Instr *getNextInstructionSequential(const Instr &InstrMeta) const;
111 bool isCFITrap(const Instr &InstrMeta) const;
121 bool canFallThrough(const Instr &InstrMeta) const;
130 const Instr *getDefiniteNextInstruction(const Instr &InstrMeta) const;
135 std::set<const Instr *>
139 bool usesRegisterOperand(const Instr &InstrMeta) const;
177 void addInstruction(const Instr &Instruction);
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H A DFileAnalysis.cpp39 using Instr = llvm::cfi_verify::FileAnalysis::Instr; typedef
121 const Instr *
123 std::map<uint64_t, Instr>::const_iterator KV = in getPrevInstructionSequential()
134 const Instr *
136 std::map<uint64_t, Instr>::const_iterator KV = in getNextInstructionSequential()
199 const Instr *
208 const Instr *NextMetaPtr; in getDefiniteNextInstruction()
230 std::set<const Instr *>
232 std::set<const Instr *> CFCrossReferences; in getDirectControlFlowXRefs()
338 const Instr &NodeInstr = getInstructionOrDie(Node); in indirectCFOperandClobber()
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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DCodeTemplate.cpp18 InstructionTemplate::InstructionTemplate(const Instruction *Instr) in InstructionTemplate() argument
19 : Instr(Instr), VariableValues(Instr->Variables.size()) {} in InstructionTemplate()
32 return Instr->Description.getOpcode(); in getOpcode()
44 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
48 return getValueFor(Instr->Variables[Op.getVariableIndex()]); in getValueFor()
52 return any_of(Instr->Variables, [this](const Variable &Var) { in hasImmediateVariables()
53 return Instr->getPrimaryOperand(Var).isImmediate(); in hasImmediateVariables()
59 Result.setOpcode(Instr->Description.Opcode); in build()
60 for (const auto &Op : Instr->Operands) in build()
H A DSerialSnippetGenerator.cpp38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr, in computeAliasingInstructions() argument
49 if (OtherOpcode == Instr->Description.getOpcode()) in computeAliasingInstructions()
71 static ExecutionMode getExecutionModes(const Instruction &Instr, in getExecutionModes() argument
74 if (Instr.hasAliasingImplicitRegisters()) in getExecutionModes()
76 if (Instr.hasTiedRegisters()) in getExecutionModes()
78 if (Instr.hasMemoryOperands()) in getExecutionModes()
81 if (Instr.hasAliasingRegisters(ForbiddenRegisters)) in getExecutionModes()
83 if (Instr.hasOneUseOrOneDef()) in getExecutionModes()
133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates() local
137 const AliasingConfigurations Forward(Instr, *OtherInstr); in appendCodeTemplates()
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H A DParallelSnippetGenerator.cpp83 getVariablesWithTiedOperands(const Instruction &Instr) { in getVariablesWithTiedOperands() argument
85 for (const auto &Var : Instr.Variables) in getVariablesWithTiedOperands()
160 const Instruction &Instr = Variant.getInstr(); in generateCodeTemplates() local
163 Instr.hasMemoryOperands() in generateCodeTemplates()
167 const AliasingConfigurations SelfAliasing(Instr, Instr); in generateCodeTemplates()
180 const auto TiedVariables = getVariablesWithTiedOperands(Instr); in generateCodeTemplates()
195 for (const auto &Op : Instr.Operands) { in generateCodeTemplates()
211 for (const auto &Op : Instr.Operands) { in generateCodeTemplates()
236 for (const auto &Op : Instr.Operands) { in generateCodeTemplates()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFeatures.h21 bool IsCPSRDead(const InstrType *Instr);
24 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
25 switch (Instr->getOpcode()) { in isV8EligibleForIT()
52 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
H A DMVETPAndVPTOptimisationsPass.cpp608 if (Instr.getNumOperands() == 0) in IsWritingToVCCR()
635 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceRegisterUseWithVPNOT()
871 if (!IsVCMP(Instr.getOpcode())) { in ReplaceVCMPsByVPNOTs()
873 if (IsWritingToVCCR(Instr)) in ReplaceVCMPsByVPNOTs()
879 PrevVCMP = &Instr; in ReplaceVCMPsByVPNOTs()
889 BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT)) in ReplaceVCMPsByVPNOTs()
890 .add(Instr.getOperand(0)) in ReplaceVCMPsByVPNOTs()
895 Instr.dump()); in ReplaceVCMPsByVPNOTs()
904 DeadInstructions.push_back(&Instr); in ReplaceVCMPsByVPNOTs()
972 auto VPNot = BuildMI(MBB, &Instr, Instr.getDebugLoc(), in ReplaceConstByVPNOTs()
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/llvm-project-15.0.7/llvm/lib/ExecutionEngine/JITLink/
H A DELF_aarch64.cpp190 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
201 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
212 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
223 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
234 if (!aarch64::isLoadStoreImm12(Instr) || in addSingleRelocation()
245 if (!aarch64::isMoveWideImm16(Instr) || in addSingleRelocation()
246 aarch64::getMoveWide16Shift(Instr) != 0) in addSingleRelocation()
256 if (!aarch64::isMoveWideImm16(Instr) || in addSingleRelocation()
257 aarch64::getMoveWide16Shift(Instr) != 16) in addSingleRelocation()
267 if (!aarch64::isMoveWideImm16(Instr) || in addSingleRelocation()
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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp197 const auto OpcodeName = Instr.Name; in isInvalidOpcode()
204 switch (Instr.Description.Opcode) { in isInvalidOpcode()
222 for (const Operand &Op : Instr.Operands) in isInvalidOpcode()
228 for (const Operand &Op : Instr.Operands) in isInvalidOpcode()
278 InstructionTemplate IT(&Instr); in generateLEATemplatesCommon()
336 Instr, ForbiddenRegisters, State, Opts, in generateCodeTemplates()
346 if (Instr.hasMemoryOperands()) in generateCodeTemplates()
350 switch (getX86FPFlags(Instr)) { in generateCodeTemplates()
396 Instr, ForbiddenRegisters, State, Opts, in generateCodeTemplates()
407 switch (getX86FPFlags(Instr)) { in generateCodeTemplates()
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/llvm-project-15.0.7/bolt/lib/Passes/
H A DAsmDump.cpp40 const MCCFIInstruction *CFIInstr = BF.getCFIFor(Instr); in dumpCFI()
61 const JumpTable *JT = BF.getJumpTable(Instr); in dumpJumpTableFdata()
204 for (const MCInst &Instr : *BB) { in dumpFunction()
206 if (BC.MIB->isPseudo(Instr)) { in dumpFunction()
207 if (BC.MIB->isCFI(Instr)) in dumpFunction()
208 dumpCFI(BF, Instr, *MAP.get()); in dumpFunction()
213 bool IsCall = BC.MIB->isCall(Instr); in dumpFunction()
235 if (BC.MIB->getJumpTable(Instr)) in dumpFunction()
236 dumpJumpTableFdata(OS, BF, Instr, BranchLabel); in dumpFunction()
237 else if (BC.MIB->isTailCall(Instr)) in dumpFunction()
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H A DPLTCall.cpp64 for (MCInst &Instr : BB) { in runOnFunctions()
65 if (!BC.MIB->isCall(Instr)) in runOnFunctions()
67 const MCSymbol *CallSymbol = BC.MIB->getTargetSymbol(Instr); in runOnFunctions()
73 BC.MIB->convertCallToIndirectCall(Instr, CalleeBF->getPLTSymbol(), in runOnFunctions()
75 BC.MIB->addAnnotation(Instr, "PLTCall", true); in runOnFunctions()
H A DVeneerElimination.cpp71 for (MCInst &Instr : BB) { in runOnFunctions()
72 if (!BC.MIB->isCall(Instr) || BC.MIB->isIndirectCall(Instr)) in runOnFunctions()
75 const MCSymbol *TargetSymbol = BC.MIB->getTargetSymbol(Instr, 0); in runOnFunctions()
81 Instr, VeneerDestinations[TargetSymbol], BC.Ctx.get())) { in runOnFunctions()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp756 IRBuilder<> B{Instr}; in narrowSDivOrSRem()
762 auto *BO = B.CreateBinOp(Instr->getOpcode(), LHS, RHS, Instr->getName()); in narrowSDivOrSRem()
763 auto *Sext = B.CreateSExt(BO, Instr->getType(), Instr->getName() + ".sext"); in narrowSDivOrSRem()
768 Instr->replaceAllUsesWith(Sext); in narrowSDivOrSRem()
769 Instr->eraseFromParent(); in narrowSDivOrSRem()
800 IRBuilder<> B{Instr}; in processUDivOrURem()
806 auto *BO = B.CreateBinOp(Instr->getOpcode(), LHS, RHS, Instr->getName()); in processUDivOrURem()
807 auto *Zext = B.CreateZExt(BO, Instr->getType(), Instr->getName() + ".zext"); in processUDivOrURem()
813 Instr->eraseFromParent(); in processUDivOrURem()
932 if (processSDiv(Instr, LVI)) in processSDivOrSRem()
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/llvm-project-15.0.7/bolt/lib/Core/
H A DExceptions.cpp533 uint8_t Opcode = Instr.Opcode; in fillCFIInfoFor()
536 switch (Instr.Opcode) { in fillCFIInfoFor()
544 Offset += CodeAlignment * int64_t(Instr.Ops[0]); in fillCFIInfoFor()
550 nullptr, Instr.Ops[0], DataAlignment * int64_t(Instr.Ops[1]))); in fillCFIInfoFor()
565 assert(Instr.Ops[0] <= Address + Function.getSize() && in fillCFIInfoFor()
567 Offset = Instr.Ops[0] - Address; in fillCFIInfoFor()
594 MCCFIInstruction::cfiDefCfa(nullptr, Instr.Ops[0], Instr.Ops[1])); in fillCFIInfoFor()
629 StringRef ExprBytes = Instr.Expression->getData(); in fillCFIInfoFor()
635 encodeULEB128(Instr.Ops[0], OS); in fillCFIInfoFor()
666 if (!decodeFrameInstruction(Instr)) in fillCFIInfoFor()
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/llvm-project-15.0.7/bolt/lib/Profile/
H A DYAMLProfileWriter.cpp51 for (const MCInst &Instr : *BB) { in convert()
52 if (!BC.MIB->isCall(Instr) && !BC.MIB->isIndirectBranch(Instr)) in convert()
56 Optional<uint32_t> Offset = BC.MIB->getOffset(Instr); in convert()
61 if (BC.MIB->isIndirectCall(Instr) || BC.MIB->isIndirectBranch(Instr)) { in convert()
63 Instr, "CallProfile"); in convert()
80 const MCSymbol *CalleeSymbol = BC.MIB->getTargetSymbol(Instr); in convert()
88 if (BC.MIB->getConditionalTailCall(Instr)) { in convert()
90 BC.MIB->tryGetAnnotationAs<uint64_t>(Instr, "CTCTakenCount"); in convert()
94 BC.MIB->tryGetAnnotationAs<uint64_t>(Instr, "CTCMispredCount"); in convert()
99 auto Count = BC.MIB->tryGetAnnotationAs<uint64_t>(Instr, "Count"); in convert()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp51 MachineInstr *Instr; member in __anon9082dfe70111::RegSeqInfo
58 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
59 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
70 return RSI.Instr == Instr; in operator ==()
184 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
185 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
224 RSI->Instr->eraseFromParent(); in RebuildVector()
227 RSI->Instr = NewMI; in RebuildVector()
311 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
359 RemoveMI(CandidateRSI.Instr); in runOnMachineFunction()
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/llvm-project-15.0.7/llvm/utils/TableGen/GlobalISel/
H A DGIMatchDagPredicate.cpp27 GIMatchDagContext &Ctx, StringRef Name, const CodeGenInstruction &Instr) in GIMatchDagOpcodePredicate() argument
30 Instr(Instr) {} in GIMatchDagOpcodePredicate()
33 OS << "$mi.getOpcode() == " << Instr.TheDef->getName(); in printDescription()
44 for (const CodeGenInstruction *Instr : Instrs) { in printDescription() local
45 OS << Separator << Instr->TheDef->getName(); in printDescription()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp90 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
94 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
96 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
98 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
112 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
113 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
115 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
116 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
132 LanaiDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
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/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugValueManager.cpp22 MachineInstr *Instr) { in WebAssemblyDebugValueManager() argument
25 if (!Instr->getOperand(0).isReg()) in WebAssemblyDebugValueManager()
27 CurrentReg = Instr->getOperand(0).getReg(); in WebAssemblyDebugValueManager()
29 MachineBasicBlock::iterator DI = *Instr; in WebAssemblyDebugValueManager()
31 for (MachineBasicBlock::iterator DE = Instr->getParent()->end(); DI != DE; in WebAssemblyDebugValueManager()
34 DI->hasDebugOperandForReg(Instr->getOperand(0).getReg())) in WebAssemblyDebugValueManager()
/llvm-project-15.0.7/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp69 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
166 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
183 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction()
186 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction()
191 switch (Instr.getOpcode()) { in getInstruction()
203 auto& Op = Instr.getOperand(1); in getInstruction()
213 auto Op = Instr.getOperand(0); in getInstruction()
214 Instr.clear(); in getInstruction()
215 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
216 Instr.addOperand(Op); in getInstruction()
/llvm-project-15.0.7/llvm/test/TableGen/
H A DPaste.td4 class Instr<int i> {
9 def Vx#NAME#PS : Instr<0>;
10 def Vx#NAME#PD : Instr<1>;
11 def Vy#NAME#PS : Instr<2>;
12 def Vy#NAME#PD : Instr<3>;
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DVectorUtils.h616 : Alignment(Alignment), InsertPos(Instr) { in InterleaveGroup()
621 Members[0] = Instr; in InterleaveGroup()
672 Members[Key] = Instr; in insertMember()
686 uint32_t getIndex(const InstTy *Instr) const { in getIndex() argument
688 if (I.second == Instr) in getIndex()
788 bool isInterleaved(Instruction *Instr) const { in isInterleaved() argument
796 getInterleaveGroup(const Instruction *Instr) const { in getInterleaveGroup() argument
797 return InterleaveGroupMap.lookup(Instr); in getInterleaveGroup()
869 assert(!InterleaveGroupMap.count(Instr) && in createInterleaveGroup()
871 InterleaveGroupMap[Instr] = in createInterleaveGroup()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DDbgEntityHistoryCalculator.h78 Entry(const MachineInstr *Instr, EntryKind Kind) in Entry() argument
79 : Instr(Instr, Kind), EndIndex(NoEntry) {} in Entry()
81 const MachineInstr *getInstr() const { return Instr.getPointer(); } in getInstr()
83 EntryKind getEntryKind() const { return Instr.getInt(); } in getEntryKind()
92 PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp280 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
284 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
287 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
291 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
295 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
299 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
304 if (isa<const LandingPadInst>(Instr)) in shouldConvertUse()
308 if (isa<const SwitchInst>(Instr)) in shouldConvertUse()
312 if (isa<const IndirectBrInst>(Instr)) in shouldConvertUse()
316 if (isa<const IntrinsicInst>(Instr)) in shouldConvertUse()
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/llvm-project-15.0.7/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch64.h52 inline bool isLoadStoreImm12(uint32_t Instr) { in isLoadStoreImm12() argument
54 return (Instr & LoadStoreImm12Mask) == 0x39000000; in isLoadStoreImm12()
63 inline unsigned getPageOffset12Shift(uint32_t Instr) { in getPageOffset12Shift() argument
66 if (isLoadStoreImm12(Instr)) { in getPageOffset12Shift()
67 uint32_t ImplicitShift = Instr >> 30; in getPageOffset12Shift()
69 if ((Instr & Vec128Mask) == Vec128Mask) in getPageOffset12Shift()
79 inline bool isMoveWideImm16(uint32_t Instr) { in isMoveWideImm16() argument
81 return (Instr & MoveWideImm16Mask) == 0x52800000; in isMoveWideImm16()
88 inline unsigned getMoveWide16Shift(uint32_t Instr) { in getMoveWide16Shift() argument
89 if (isMoveWideImm16(Instr)) { in getMoveWide16Shift()
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